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SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

Renu Vibha 21 days ago

Curious about S-Parameters, Insertion Loss, or Return Loss?

Bring your questions and join our upcoming Cadence Sigrity SI/PI Live Experts Session.

Learn proven analysis techniques, hear practical use cases, and interact directly with Cadence specialists.

Topic - Pre-layout Simulations covering Aurora Workflows, Topology Workbench (Pre-layout), Power SI ERC

Participate here on August 19^th at 7:30-8:30PM IST.

Bring your questions. Leave with answers

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AK20250609765 4 days ago in reply to EDAHut +1

Thank you for the question. To maintain the validity of pre-layout signal integrity (SI) results when the PCB stackup changes during the design cycle, follow these steps: Correctly Model Devices: Ensure…

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0 EDAHut 4 days ago

Where does the handoff from schematic driven topologies to physical layout in Cadence Sigrity Aurora break down the most ?
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0 EDAHut 4 days ago in reply to EDAHut

During pre layout engineer creates a tuned LPDDR4 memory topology with specific termination resistors using generic schematic nodes … when transferring this to physical layout , mismatching pin names between the schematic symbols and the actual layout footprints break the net connectivity mapping in Aurora .. this completely resets the constraint manager rules, forcing the layout team to manually reassign routing constraints from scratch
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0 AK20250609765 4 days ago in reply to EDAHut

The handoff typically breaks down when the logical connectivity used during topology creation no longer matches the physical implementation. Pin-name mismatches, component-definition differences, or connectivity mapping issues can prevent correct constraint transfer, forcing manual re-assignment of routing constraints in the layout flow. Maintaining consistent schematic-to-layout mapping is key.
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0 AK20250609765 4 days ago in reply to EDAHut

The handoff typically breaks down when the logical connectivity used during topology creation no longer matches the physical implementation. Pin-name mismatches, component-definition differences, or connectivity mapping issues can prevent correct constraint transfer, forcing manual re-assignment of routing constraints in the layout flow. Maintaining consistent schematic-to-layout mapping is key.
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