• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    Differential pair constraint region problem Locked

    17646 views
    5 replies
    Latest over 7 years ago
    by steve
  • Discussion

    how to enlarge simulation time limit of ncsim? Locked

    17971 views
    2 replies
    Latest over 7 years ago
    by galenxiao
  • Discussion

    How to update the netlist (input.scs) from extracted view after QRC extraction Locked

    18265 views
    10 replies
    Latest over 7 years ago
    by Mamad
  • Discussion

    How to do Components placement movement in a particular angle from existing position when we don't know the exact XY locations to where we need to move Locked

    1845 views
    3 replies
    Latest over 7 years ago
    by Tmills
  • Discussion

    ihdl vs netExpr Locked

    15292 views
    0 replies
    Started over 7 years ago
    by drdanmc
  • Discussion

    How to use ocnDspfFile with case_sensitive port/net names Locked

    1167 views
    2 replies
    Latest over 7 years ago
    by jsundermeyer
  • Discussion

    Systemverilog interfaces over hierarchical boundaries Locked

    15796 views
    0 replies
    Started over 7 years ago
    by pvuc
  • Discussion

    Updating Net Names in Layout XL Locked

    8266 views
    2 replies
    Latest over 7 years ago
    by Andrew Beckett
  • Discussion

    Error about Environment Variable settings Locked

    27239 views
    17 replies
    Latest over 7 years ago
    by wgtkan
  • Discussion

    How to Disable visiblity of only Dynamic Copper shape Locked

    19076 views
    6 replies
    Latest over 7 years ago
    by chadga
  • Discussion

    How to create custom bus taps Locked

    13634 views
    0 replies
    Started over 7 years ago
    by Shells
  • Discussion

    Parasitic exclusion Locked

    18054 views
    5 replies
    Latest over 7 years ago
    by manudupouy
  • Discussion

    Run analogLib/fourier before stop time Locked

    2153 views
    3 replies
    Latest over 7 years ago
    by Andrew Beckett
  • Discussion

    Layout pcell label tinkering Locked

    15945 views
    3 replies
    Latest over 7 years ago
    by Andrew Beckett
  • Discussion

    Device spacing in modgen using SKILL Locked

    16285 views
    4 replies
    Latest over 7 years ago
    by Andrew Beckett
<>

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information