Are there any semiconductor vendor-supplied models in IC stream?

This is a very basic but also a all encompassing question
which is not answered in one or two sentences and you better
look for local support than posing to a forum.

If you intent to use Spectre as your circuit simulator
please refer to the "Virtuoso Simulator Circuit Components
and Device Models Manual"
<installation_dir>/doc/spectremod/spectremod.pdf
and to the
"Virtuoso Spectre Circuit Simulator User
Guide"
<installation_dir>/doc/spectreuser/spectreuser.pdf

Semiconductor vendor models, you got in principal form you
Silicon foundry. For education there are resources
like
 Euriopractice  http://www.europractice-ic.com/
 MOSIS http://www.mosis.com/
 NSCU http://www.eda.ncsu.edu
 
The .so files a C++ shared libraries and have nothing to do
with  simulator models at all.

Bernd

 Just for completeness, if you do "spectre -h" you'll see a bunch of available components listed with a "*" next to them. For example:

     bjt301*          bjt500*          bjt500t*         bjt503*
    bjt504*          bjt504t*         bjt3500*         bjt3500t*
    bjtd504*         bjtd504t*        bjtd3500*        bjtd3500t*

These come from the shared libraries you've listed. The idea is that the code which defines the model equations can be loaded via a shared library. This is used by some customers to add custom models (via the C Model Interface) into spectre and other Cadence simulators. There are also some models which aren't listed in the spectre -h which come from these.

However, the key thing is that this is just the model code - not the model parameters. To use these models for a real process, you'd need a model card which will define appropriate sets of parameters to represent the measured and qualified behaviour of a real device, as Bernd said.

Regards,

Andrew.

 Hi Andrew,

 Thats indeed what I missed.
"The .so files a C++ shared libraries and have nothing to do
with  simulator models at all."
This is of courses a bit misleading as the .so files are related to the
model implementation as you said.
It is always a pleasure to read your detailed explanations ;-).

Bernd

Andrew,

Thanks for the clarification.  I am just curious why there is no published interface for these libraries; these files are all binary.  Perhaps, they are in the install tree but I have not found them or Cadence will provide them if we ask.

Why is there none true 3-terminal MOS symbols in analogLib?  I see nmos and nmos4, but the former is programmable bulk node.  The models we downloaded from discrete IC vendors all have three terminals.  We ended up copying nmos component and change CDF info to netlist out only three terminals.  If you have cleaner solution, please share.

Regards,

Achilles

Hi Achilles,

Why does there need to be a "published interface" for these files? They are part of the software installation, and simply part of the way that the simulator executable is delivered. There is a C Model Interface which is available to customers who purchace it (it's a licensed product) which allows custom models to be written, but that's relatively rare and typically only used by large customers who have existing proprietary device models (not proprietary device model parameters, but proprietary model implementations). 

We don't document any of the other shared libraries which are part of the software installation, so there's no reason why these should be either. The "interface" to them is to define (for example):

model nch psp102 type=n tox=3e-9 ...

Just as you would any other model.

The reason why the analogLib components netlist four terminals (even for the 3 terminal components) is because in spectre all (as far as I know) MOS models have 4 terminals. Some models (e.g. jfet, bjt etc) have an optional 4th terminal - but from looking at mos1, mos2, mos3, bsim3v3, bsim4, psp102, they all expect a bulk node. Which model are you using that requires only 3?

analogLib is really just a sample library. Most design kits would provide specific components to netlist whatever model names that are being provided by that design kit, but it's straightforward enought to customise to suit your needs.

Regards,

Andrew.

The model interfaces are documented
do a
 spectre -h component
e.g.
 spectre -h bsim3v3
and you will get a description how to use the
mode the "Instance Parameters" define the interface to
the design entry.

A MOS transistor on silicon allways have a 4th terminal
which is the silicon itself, mostly called substrate or bulk.

If you want to simulate discrete transistors with Spectre
your are probably going for the wrong approach.
You rather should look for some PSpice or LTspice or
some equivalent simulator for discrete elements.

Bernd

Hi Andrew,

I understand once you says it is a licensed product.  What I meant is the API for those provided libraries.

Our flow is IC centric, we have our IC plus extra external discrete devices to simulate the system level where the IC will be put in, so LTSpice, Pspice is useless.  Th

My model would be as follows.  The discrete IC are 3-terminals; so are their models.

.SUBCKT SPP04N80C3_L0  drain  gate  source

.ENDS  SPP04N80C3_L0

Achilles,

The compiled model interface is a product which provides the means to create such shared libraries - in other words, it describes the available API in the simulator, and the interface to which the compiled model code must conform. There is no public API for any other tool to use these shared libraries - they are solely for the use of Cadence simulators, so there is absolutely no benefit in any user knowing how to interface to them.

From your example (which I will edit to remove the contents, as I doubt you are allowed to post it on a public web site as it is probably the property of Infineon - please be careful about posting proprietary information such as this without permission from the vendor), it is a 3 terminal subckt. Equally possible would  be a 4 terminal, or 5 terminal, or 6 terminal model - depending on the discrete component. If you have different types of devices, there is always likely to be some customization to the symbol and CDF needed to suit that.

Given that most of the transistor models that users would use with analogLib components are on-chip (rather than discrete), it makes sense for the examples to all match those. And it's trivial to take the examples in analogLib and adapt them to whatever you actually need - all you have to do is copy the nmos or pmos component and change the CDF and remove the bulk terminal on the spectre view (or you could copy the symbol across to the spectre view, say).

Best Regards,

Andrew.

There once was a relate Blog post, maybe this helps too
http://www.cadence.com/Community/blogs/rf/archive/2009/01/07/tip-of-the-week-how-to-simulate-a-subcircuit-netlist-with-spectre-in-ade.aspx?postID=13758

Also it is possible to use analogLib/nmos and
add a 4th terminal as dummy to your subckt,
 e.g. .SUBCKT comp_name  drain gate source bulk
Where the 4th term is required for netlisting, but will have
no effect in the subckt.

Bernd