Stats

  • Locked Locked
  • Replies 1
  • Subscribers 92
  • Views 13004
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to avoid a group of cell from getting optimised

crystee
The thing is the design contain some memory, but memory complier is not available for hardening the memory. While optimising the rest of the logic, the memory which is realised as flops are also optimised. Reason is SoC encounter see these flops as just instances/standard cell.
 As a result, timing cant be closed at desired frequency & is also leading to very high setup & hold violations.

So how to optimise the rest of the design without touching the memory part.

  • set_dont_touch

    set_dont_touch object_list [true | false]

    Prevents the specified object from being modified during optimization.

    When you specify a net, all the connecting instances are affected by the set_dont_touch command.

    Parameters

     


    true | false

    Sets or removes the set_dont_touch attribute for the specified object_list.

    Default: true

    object_list

    Specifies the list of instances, nets, library cells, or submodules.

     

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.