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Mixed language simulation
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Mixed language simulation
Jayakirthi
over 11 years ago
Hi, Can anyone help me
how to simulate UVM testbench with SystemC design at pin level in cadence tool
.. How to set UVM lib path and Systemc path and compile it.... please suggest what to refer or give an example
I am new to cadence tools, your information will be very helpfull.
Thank you vry much in advance
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