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Look up table generation of TFET using verilog-A models in CADENCE

Kabes

Hi,

I have implemented a Tunnel FET device using SILVACO Atlas and extracted all the device parameters for the purpose of look up table generation.

Now, I want to define a model and schematic for the device under consideration in the CADENCE simulator and test it for inverter and ring oscillator circuits.

The issue is how to include look up table based Verilog-A models in CADENCE?

Please help me by providing steps/manuals to create a lookup table in Cadence of new device
Further I want to perform the dc and transient responses of the TFET-based inverter and ring oscillator circuits using the Verilog-A model in the CADENCE tool.

Please help/guide me in this regard I shall be thankful to you.
regards!
Parents
  • Which Cadence tool? There is no tool called "Cadence" and there's more than one simulator that you might be talking about.

    This forum is not for technical questions - it's for feedback, suggestions and questions about the forum itself. So by knowing the tool (and ideally version), I can redirect your question to an appropriate forum.
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  • Which Cadence tool? There is no tool called "Cadence" and there's more than one simulator that you might be talking about.

    This forum is not for technical questions - it's for feedback, suggestions and questions about the forum itself. So by knowing the tool (and ideally version), I can redirect your question to an appropriate forum.
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