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LVS warning related with sampling conflicts

I did my layout but i get "WARNING: Stamping conflict in SCONNECT - Multiple source nets stamp one target net.
Net GND is selected for stamping.
Rejected nets: 86 87"   this kind of error.

I added the net 86 as a picture.

But i didnt understand what am i doing. If you help me, i will be very happy. Thank you so much.

  • You haven't provided a great deal of information (such as which physical verification tool you're using or which technology you're using - the rule will be specific to whichever process/PDK you're using).

    It looks however from your picture that you have a transistor with three guard rings around it. I think the middle one is a substrate guard ring and so is connecting to the substrate from metal - and it appears that that metal is floating. I'm not sure what  "net 86" is in your picture, but given that the substrate is conducting, stamping errors like this are stating that you have more than one net connected down onto the substrate.


  • Sorry for late reply. I deleted multiple links that connect to down onto the substrate. I made the connections by connecting one of the connections to the outp of the upper capacitor and the other to the outn of the lower transistor (like the picture I added to my new post), but I still get the same warning. 

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