Hi,
I have a few questions regarding Lab 3-3: Dynamic Comparator Noise Characterization in ADC Verification RAK.
1) Why is the beat period in PSS chosen to be twice the comparator clock cycle? Is there a specific reason for selecting two clock cycles instead of just one?
2) In this Lab, the value of different input (vid) and compartor gain (gain) are set to 500uV and 100V/V, which sets the sampling point to where the comparator differential output levels areseparated by 50mV. I'm curious about how "vid" and "gain" were initially chosen, as different values for "vid" and "gain" can significantly affect the pnoise result.
3) Here the sampled(jitter) is chosen to be the Noise Type in pnoise. However, with time-average, the noise can be referred to the input automatically. How does the simulator decide the gain of the comparator and why time-average is not used in the comparator noise analysis?
Thank you in advance.
Shu-Yan