Hi Cadence Community,
I am currently working with Cadence's 45nm technology and have encountered a peculiar issue with the NMOS High-Voltage Threshold (HVT) transistor. Specifically, I'm observing an unexpected relationship between the oxide thickness and the saturation current.
Here's the situation:
When I increase the oxide thickness, the saturation current increases.
Conversely, when I decrease the oxide thickness, the saturation current decreases.
From my understanding, this behavior is counterintuitive since typically, a thicker oxide would lead to a reduction in gate capacitance and consequently a decrease in the drive current. Conversely, a thinner oxide should enhance the gate control over the channel, thereby increasing the drive current.
Has anyone else encountered this issue or could provide insights into what might be causing this anomalous behavior? I am curious if there are any specific aspects of the 45nm technology node or the HVT transistors that might explain this phenomenon. Any suggestions for further investigation or potential solutions would be greatly appreciated.
Thank you in advance for your help!
How are you varying the oxide thickness? It's not a parameter on the device (at least I don't think it is).
Bear in mind that this is a fictional process, so it is intended to be representative, not exactly behaving as a real life device would (so in other words, the models are fitted on some fictional curves, and may not behave correctly if you're editing the model files).
Andrew
I am varying the oxide thickness in model file.
How to vary the oxide thickness? But all the other transistors showing expected behavior like HVT PMOS,LVT PMOS and LVT NMOS. Thanks for your reply Sir.