High-Voltage MOSFET Body Diode Behavior and Extraction Issues in Post-Layout Simulation

Hello,

I’m working on a design using a TSMC 180nm High Voltage (GEN2) process. The devices in use, according to the PDK model files, include internal body diodes as part of their structure.

Setup:

• VDD = 20V supply
• Layout passes DRC, LVS, and ANN
• SUB terminals for both NMOS and PMOS are connected to GND and VDD respectively

Issues Encountered:

• In Calibre PEX, I see warnings like:
  
  • “Area for diode cannot be 0.0, reset to 1e-12”
  • “Layout instances ignored due to invalid master”
• In Assura layout extraction, I can Diode noted “unmatched”
• In Spectre post-layout simulations, DC and transient behavior significantly diverges from schematic-level results.

I suspect that leakage through internal body diodes at high voltage (20V) is causing simulation instability or unexpected current paths—possibly due to how the substrate terminals are connected or how the extraction tool interprets the parasitics.

Questions:

1. What is the recommended way to connect SUB terminals in high-voltage devices to avoid body diode conduction or leakage?
2. How can I configure Calibre PEX (or Assura) to extract accurate area/perimeter values and avoid diode mismatch warnings? Since we cannot control or set the internal Diode no matter in schematic or layout.
3. Is there a specific LPE or netlisting flow required to properly handle HV parasitics and diode modeling in this process?

Any help on preventing diode-related leakage and ensuring post-layout accuracy at high voltage mosfets or any experience about the HV PDK would be greatly appreciated.