UVM Adapter for Pipelined protocols like AHB, AXI etc

Hello,

I have been running this `uvm_reg_hw_reset_seq` sequence for the AHB protocol. My UVM Adapter looks like:

Issue: When I use basic reg.write, my write access are working well, as that is managed by the driver i.e. once adapter gives the packet to the driver, the driver supplies the address and the control signals to the DUT on the first clock cycle and then the write data on the next clock cycle. But when I am performing the read operation, somehow the UVM adapter is reading the data at the same clock cycle where read address + Controls are supplied and this is triggering read failure messages from the `uvm_reg_hw_reset_seq` sequence. What should I modify in the driver/sequencer/adapter so that the UVM adapter can read the data on the next cycle instead of the same clock cycle.

Just FYI: The waveforms of the read operation are correct, it is just the Adapter and the `uvm_reg_hw_reset_seq`. The AHB Driver + AHB Monitor is fully proven and verified to be working correctly.