For analog design, I have not seen too many people make use of pcells for schematics or symbols.Are you using pcells for schematics or pcells, especially for analog design? If so, what is the basic function of the pcell? Why did you choose a pcell instead of a static cell?Thanks!
I have created both schematic and symbol pcells. Some examples:I have a transistor symbol which can either be a 3 or 4 terminal mosfet, controlled by a property on the pcell. If the user chooses 3 terminals, then the 4th terminal is found via an inherited connection terminal on the stopping (e.g. spectre) view - but they don't need to wire it up. If the user chooses 4 terminals then all 4 terminals are present on the symbol.Another example is a component for driving a bus with a constant value. This has parameters for the value and the bus width. This is implemented with both a schematic and a symbol pcell. The symbol pcell merely changes the terminal/pin to be a bus with variable width; the schematic pcell instantiates a variable number (depending on the bus width parameter) of "cds_thru" components to create connections from either a high input or a low input to the particular bit of the bus - which connection is made depends on the value parameter of the pcell.Another schematic pcell is for a series-connected resistor. I wanted a resistor with an "s-factor", so that the voltage dependency on a number of series connected resistors could be modelled properly (there are other ways of solving this, but this was more of an illustration). So it divides the resistor value by the s-factor, and places s resistors with that divided value, connected in series.That's some simple examples of what they can be useful for.Note with schematic pcells there's no need to create the graphical representation of the schematic - just the connectivity information will do.Regards,Andrew.
In a previous life, we were working with a process which was yet to be fully qualified, and for which there were no PDKs, so I wrote the pCells for layout and schematics.
Using common code between the schematic symbol and layout views allowed me to know the exact dimensions of the component given appropriate parameters (FET width and length, resistor value, capacitor value), from which parasitic effects could be determined and annotated onto the device for netlisting (via CDF parameters) eg. FET AS/AD/PS/PD, resistor parasitic cap, capacitor bottom plate cap, etc.
We had very good agreement between schematic simulation and RCX extracted simulation (and final silicon) at and above 6GHz, and our design cycles were tighter because we didn't need to go around the RCX loop as often.
With proper parameterized spectre/spice models, or a decent PDK, you don't need to do this. But if you want to work outside those models, nothing beats it.