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  3. schematic and symbol pcells?

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schematic and symbol pcells?

archive
archive over 19 years ago

For analog design, I have not seen too many people make use of pcells for schematics or symbols.

Are you using pcells for schematics or pcells, especially for analog design?  If so, what is the basic function of the pcell?  Why did you choose a pcell instead of a static cell?

Thanks!


Originally posted in cdnusers.org by m27315
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  • archive
    archive over 19 years ago

    In a previous life, we were working with a process which was yet to be fully qualified, and for which there were no PDKs, so I wrote the pCells for layout and schematics. Using common code between the schematic symbol and layout views allowed me to know the exact dimensions of the component given appropriate parameters (FET width and length, resistor value, capacitor value), from which parasitic effects could be determined and annotated onto the device for netlisting (via CDF parameters) eg. FET AS/AD/PS/PD, resistor parasitic cap, capacitor bottom plate cap, etc. We had very good agreement between schematic simulation and RCX extracted simulation (and final silicon) at and above 6GHz, and our design cycles were tighter because we didn't need to go around the RCX loop as often. With proper parameterized spectre/spice models, or a decent PDK, you don't need to do this. But if you want to work outside those models, nothing beats it. cheers, -steve


    Originally posted in cdnusers.org by stevea
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  • archive
    archive over 19 years ago

    In a previous life, we were working with a process which was yet to be fully qualified, and for which there were no PDKs, so I wrote the pCells for layout and schematics. Using common code between the schematic symbol and layout views allowed me to know the exact dimensions of the component given appropriate parameters (FET width and length, resistor value, capacitor value), from which parasitic effects could be determined and annotated onto the device for netlisting (via CDF parameters) eg. FET AS/AD/PS/PD, resistor parasitic cap, capacitor bottom plate cap, etc. We had very good agreement between schematic simulation and RCX extracted simulation (and final silicon) at and above 6GHz, and our design cycles were tighter because we didn't need to go around the RCX loop as often. With proper parameterized spectre/spice models, or a decent PDK, you don't need to do this. But if you want to work outside those models, nothing beats it. cheers, -steve


    Originally posted in cdnusers.org by stevea
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