[SOLVED] Verilog-AMS code doesn't compile with genvar

I am writing a verilog-ams model for an 8 bit ADC. The code is derived from section 4.5.8 example 2 of vams2.3.1 reference. However, the use of genvar gives an error:

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Error found by spectre during AHDL compile.
    ERROR (VACOMP-1149):
        "/.../adc_8bit/veriloga/veriloga.va", line
        27: Genvar loop evaluation failed. Check whether `/usr/bin/perl' is
        available.
    ERROR (VACOMP-1816): Exiting AHDL compilation.
Internal error found in spectre during AHDL compile, during generation of
        Artist DPLs.  
Encountered a critical error during simulation. Submit a Service Request via
        Cadence Online Support, including the netlist, the Spectre log file,
        the behavioral model files, and any other information that can help
        identify the problem.
    FATAL (SPECTRE-18): Segmentation fault.
/uusoc/facility/cad_tools/Cadence/MMSIM_13.11.176_lnx86/tools/bin/spectre[80]: .: line 1076: 22896: Abort

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The error is in the first line that uses genvar, and complains about "usr/bin/perl". Any clues to fixing this?

Here is my complete code

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`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns / 1ps

module adc_8bit (out, in, clk, vref, avdd, agnd, ibias) ;
input in, clk, vref, avdd, agnd, ibias;
output [0:7] out;
electrical in, clk, vref, avdd, agnd, ibias;
electrical [0:7] out;

real vdd, ref;
real sample;
integer result[0:7];
//integer i;
genvar i;

analog begin

 vdd = V(avdd) - V(agnd);
 ref = V(vref) - V(agnd);
        @(cross(V(clk) - vdd/2, +1)) begin
                sample = V(in);
                for ( i = 7; i >= 0; i = 1-1) begin
                        if (sample > ref) begin
                                result[i] = 1;
                                sample = sample - ref;
                        end
                        else begin
                                result[i] = 0;
                        end
                        sample = 2.0*sample;
                end
        /*
                for ( i = 7; i >= 0; i = 1-1) begin
                        V(out[i]) <+ transition(result[i], 0, 10n);
                end
        */
                V(out[7]) <+ transition(result[7], 0, 10n);
                V(out[6]) <+ transition(result[6], 0, 10n);
                V(out[5]) <+ transition(result[5], 0, 10n);
                V(out[4]) <+ transition(result[4], 0, 10n);
                V(out[3]) <+ transition(result[3], 0, 10n);
                V(out[2]) <+ transition(result[2], 0, 10n);
                V(out[1]) <+ transition(result[1], 0, 10n);
                V(out[0]) <+ transition(result[0], 0, 10n);
        end

endmodule

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