[SOLVED] unable to compile with genvar variable in veriloga

First of all, please read the forum guidelines. These ask you not to post the same question in multiple forums. I will answer your issue here and add a cross-reference in the other post.

The cause of the problem (unfortunately it gives a rather cryptic message) is that your for loop is incorrect. You have:

                for ( i = 7; i >= 0; i = 1-1) begin

this means that you have an infinite loop. because i is set to 0 at the end of each iteration and so will never end. A genvar causes it to attempt to expand the loop at compilation time (or elaboration time - not entirely sure which off the top of my head) and so it can't succeed. The message about perl is misleading in this case.

In the code as it stood, you could have left it as an integer rather than a genvar because there's no need for it to be a genvar (only the commented out part needs a genvar). However, that reveals that  you have an end statement missing. This needs to end the begin for the @cross statement, because the contribution statements need to be outside of the @cross block as they need to be present on every iteration, not just during the cross events. If you'd fixed the missing end and left it as an integer rather than genvar, you'd have seen it hang at simulaton time because of the infinite loop.

Anyway, by fixing the for loop and uncommenting the for loop around the contribution statements (and fixing the for loop there too as that was also incorrect) and inserting the missing end, I get:

`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns / 1ps

module adc_8bit (out, in, clk, vref, avdd, agnd, ibias) ;
input in, clk, vref, avdd, agnd, ibias;
output [0:7] out;
electrical in, clk, vref, avdd, agnd, ibias;
electrical [0:7] out;

real vdd, ref;
real sample;
integer result[0:7];
//integer i;
genvar i;

analog begin

 vdd = V(avdd) - V(agnd);
 ref = V(vref) - V(agnd);
        @(cross(V(clk) - vdd/2, +1)) begin
                sample = V(in);
                //for ( i = 7; i >= 0; i = 1-1) begin
                for ( i = 7; i >= 0; i = i-1) begin
                        if (sample > ref) begin
                                result[i] = 1;
                                sample = sample - ref;
                        end
                        else begin
                                result[i] = 0;
                        end
                        sample = 2.0*sample;
                end
        end
        for ( i = 7; i >= 0; i = i-1) begin
                V(out[i]) <+ transition(result[i], 0, 10n);
        end
        /*
                V(out[7]) <+ transition(result[7], 0, 10n);
                V(out[6]) <+ transition(result[6], 0, 10n);
                V(out[5]) <+ transition(result[5], 0, 10n);
                V(out[4]) <+ transition(result[4], 0, 10n);
                V(out[3]) <+ transition(result[3], 0, 10n);
                V(out[2]) <+ transition(result[2], 0, 10n);
                V(out[1]) <+ transition(result[1], 0, 10n);
                V(out[0]) <+ transition(result[0], 0, 10n);
        */
        end

endmodule

which works correctly.

Regards,

Andrew.

First of all, please read the forum guidelines. These ask you not to post the same question in multiple forums. I will answer your issue here and add a cross-reference in the other post.

The cause of the problem (unfortunately it gives a rather cryptic message) is that your for loop is incorrect. You have:

                for ( i = 7; i >= 0; i = 1-1) begin

this means that you have an infinite loop. because i is set to 0 at the end of each iteration and so will never end. A genvar causes it to attempt to expand the loop at compilation time (or elaboration time - not entirely sure which off the top of my head) and so it can't succeed. The message about perl is misleading in this case.

In the code as it stood, you could have left it as an integer rather than a genvar because there's no need for it to be a genvar (only the commented out part needs a genvar). However, that reveals that  you have an end statement missing. This needs to end the begin for the @cross statement, because the contribution statements need to be outside of the @cross block as they need to be present on every iteration, not just during the cross events. If you'd fixed the missing end and left it as an integer rather than genvar, you'd have seen it hang at simulaton time because of the infinite loop.

Anyway, by fixing the for loop and uncommenting the for loop around the contribution statements (and fixing the for loop there too as that was also incorrect) and inserting the missing end, I get:

`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns / 1ps

module adc_8bit (out, in, clk, vref, avdd, agnd, ibias) ;
input in, clk, vref, avdd, agnd, ibias;
output [0:7] out;
electrical in, clk, vref, avdd, agnd, ibias;
electrical [0:7] out;

real vdd, ref;
real sample;
integer result[0:7];
//integer i;
genvar i;

analog begin

 vdd = V(avdd) - V(agnd);
 ref = V(vref) - V(agnd);
        @(cross(V(clk) - vdd/2, +1)) begin
                sample = V(in);
                //for ( i = 7; i >= 0; i = 1-1) begin
                for ( i = 7; i >= 0; i = i-1) begin
                        if (sample > ref) begin
                                result[i] = 1;
                                sample = sample - ref;
                        end
                        else begin
                                result[i] = 0;
                        end
                        sample = 2.0*sample;
                end
        end
        for ( i = 7; i >= 0; i = i-1) begin
                V(out[i]) <+ transition(result[i], 0, 10n);
        end
        /*
                V(out[7]) <+ transition(result[7], 0, 10n);
                V(out[6]) <+ transition(result[6], 0, 10n);
                V(out[5]) <+ transition(result[5], 0, 10n);
                V(out[4]) <+ transition(result[4], 0, 10n);
                V(out[3]) <+ transition(result[3], 0, 10n);
                V(out[2]) <+ transition(result[2], 0, 10n);
                V(out[1]) <+ transition(result[1], 0, 10n);
                V(out[0]) <+ transition(result[0], 0, 10n);
        */
        end

endmodule

which works correctly.

Regards,

Andrew.