Today at CadenceLIVE Taiwan, we announced Integrity 3D-IC Platform. This is a new automated approach to doing 3D chiplet-based designs. The trend towards large high-performance systems being implemented with multiple chiplets has been going on for some time. For example, see my post from a couple of years ago HOT CHIPS: Chipletifying Designs or from earlier this summer when I wrote about the most complex chiplet-based design I've ever seen, Intel's Ponte Vecchio, in HOT CHIPS: Two Big Beasts.
Integrity 3D-IC provides:
I could write an entire post on why you might want to do a design based around chiplets (also sometimes called tiles). In fact, I have already written a few over the years. The most recent were John Park's Webinar on Chiplets and Brian Jackson Introduces a Mystery Product at IMAPS (Shh, It's OrbitIO). In the second of those posts, I gave a list of most of the motivations for using a chiplet-based design as opposed to monolithic integration.
Some designs are too big for a single reticle, so you can't do it
Some things (analog, RF) are impossible to do in the most advanced nodes, so you can't do it
IP availability (e.g., SerDes or DDR or PCIe) may not yet be available when you need them, so you can't do it yet
It makes no sense to design an entire system in an advanced node when only some parts of the system require it or can take advantage of it, so it's too expensive to do it
Small die improve yield, so it's too expensive to do it
You can't get enough memory on the monolithic die, so you can't do it
Another motivation that I didn't mention in that post is that you probably don't want to have testchip for your most advanced SerDes (such as 112G) on the critical path for the whole design, especially if it is already functional and characterized in the prior process generation.
The solution to these problems is to go into the third dimension. For several years now, design groups have been doing this, but using a flow where each of the chiplets has to be designed separately and then the system carefully stitched together without a lot of automation. Today, that automation has arrived.
Cadence’s Integrity 3D-IC platform is an integrated solution for planning, implementation, and signoff of heterogeneous and homogenous 2.5D and 3D stacked designs that allow integration of multiple chiplets. The platform consists of multiple modular sub-flows and combines elements of system-level planning and analysis with actual physical implementation and early analysis, achieving big productivity improvements for 3D-IC design.
The diagram above shows how Integrity 3D-IC is architected. In the center is the new Integrity Platform Database. This is multi-technology, in the sense that each chiplet in the design can be in a different process with a different PDK.
On the left are the analysis tools, all of which have been updated to support chiplet-based designs. In particular, Tempus has been updated with Rapid Automated Inter-Die analysis. This reduces the number of signoff corner combinations and so reduces the time required to perform static timing analysis. Tempus ECO has been extended to handle changes on multiple-chiplets. Thermal analysis with Celsius is another area that is especially critical for chiplet-based designs, since any chiplet on top of another chiplet acts as a thermal barrier, plus it is good to ensure that any hot area on one chiplet does not overlap a similarly hot area on another.
In the top center is the Innovus-based floorplanning and implementation, now with all the capabilities of OrbitIO also included to allow for complex design planning.
On the right are the designs that Innovus cannot handle natively and whose implementation is handled by co-design with other tools in the Cadence portfolio:
Integrity 3D-IC is the industry's first integrated platform enabling system-driven PPA. PPA stands for Performance, Power, and Area. Actually, Area should really be cost, since there are other costs than just the size of the chiplets in this sort of design, but the PPA letters are now so ingrained that it would be hard to change.
In some multi-chiplet designs, the disaggregation of chiplets is pre-decided, but in some other cases, some power, performance, and area (PPA) improvement exploration is possible on a standard design by splitting the 2D design into a 3D design. One method to do this manually is based on the architecture to make a 3D stacked design by identifying which logical partitions go on the top die and which go on the bottom die. Another technique that’s gaining popularity is to have all macros from the design in one chiplet and all the standard cells in another chiplet. A special case of this is when all the macros are memories and so you end up with one "logic" chiplet and one "memory" chiplet. Putting memory on logic like this reduces memory latency significantly. Typically, the partition cannot be quite this clean since test logic for the memory is best put on the memory chiplet.
Although the design pre-dates Integrity, a great example of this is Arm's experimental implementation of a Neoverse N1 done using this style of partitioning and described in my post Taking Arm Neoverse into 3D with Digital Full Flow. This design would be much easier to implement today since Integrity 3D-IC supports this sort of design directly in its database, and then Innovus and the signoff tools can work directly on it.
Watch Chin-Chi Teng present Integrity-3D (2.5 minutes):
See Michale Jackson discuss how RAID reduces the number of corners (3 minutes):
See Don Chan talking about System-PPA in the Integrity unified environment (3 minutes):
See the Integrity 3D-IC Platform product page.
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