Cadence Runs on AMD Processors, and AMD Uses Cadence to Design Those Processors

21 Mar 2022 • 3 minute read

30 years of computational software One challenge in EDA and the design of microprocessors is that the next generation of processors has to be created using the previous generation of processors and the previous generation of EDA. Only then will the new more powerful processors be available to take advantage of the design of the generation after that. It is actually even more inter-related than that since often a new semiconductor process generation is involved. If the process has some new features (via pillars, say, or buried power rails) then there are three moving parts: creating the semiconductor process, adding support for the process to the EDA tools, and designing the next-generation processor that takes advantage of those new process features. I've read that tuning a steel drum, one of those Caribbean drums made out of old oil drums, is really hard since each time you use a hammer to alter one of the notes, it affects all the ones around it. Developing a next-generation processor, on a next-generation process, with next-generation EDA tools is a bit like that. Developing the tools requires test cases, but there can't be any test cases until the tools support the new process features (although they will, for sure, be buggy...did I say there were no test cases?). Another challenge is that each design is larger than the previous one, so the capabilities of Cadence's computational software has to be constantly re-invigorated.

None of these are new problems, they have been the way of life since I've been involved in semiconductors and EDA. In fact, in the late 1990s and early 2000s, between architectural developments in processors and Moore's Law still in full swing, processors were improving in performance by about 50% per year. There are still architectural improvements, but nothing completely new: wider reorder buffers, wider instruction decode, better branch prediction, bigger caches, and so on. But nothing as dramatic as adding the first caches, switching from scaler to super-scalar, from in-order to out-of-order execution, and all the features that we take for granted in a modern high-end processor. At least, if we look under the hood. If none of these words made sense to you, you might want to read my post How Do Out-of-Order Processors Work Anyway?

Advanced 3D Packaging

AMD was one of the first companies to make extensive use of advanced packaging, 2.5D. It has been a regular presenter of its technology at HOT CHIPS (held each August). I wrote about this in my posts:

Of course, AMD processors are used in some data centers and so Cadence tools run on them. We also run on Intel processors and Arm-based processors such as AWS's Gravitron. They are now up to Gravitron 3 with, presumably, the next-generation Graviton 4 being designed at Annapurna Labs on Gravitron 3 servers. Design the next generation on the previous generation. As far as I know, all current-generation advanced processors are on 5nm processes (or 4nm, which to my understanding is an optical shrink of essentially the same process). I assume the next generation will all be on 3nm, depending on availability from the three foundries that are working on bringing up such a process.

AMD EPYC 7003

amd epyc 7003

Last week, AMD announced their EPYC 7003 processor, with 3D V-cache technology, and Cadence's computational software is architected to take advantage of the large amount of cache and high-bandwidth access.

Cadence and AMD Video

Here is a Cadence/AMD video on how we have worked together in the way described in this post (2 minutes 20 seconds):

And here is AMD's own video on the EPYC 7003 (1 minute, and already over 7M views):

Tuning a Steel Drum

It's not really germane to this post, but since I used tuning a steel drum as an analogy at the start of this post, I took a look on YouTube, and of course there are videos of how to tune a steel drum. So if you have half an hour to kill, get a coffee and enjoy this video.

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