Rapid Adoption of the Arm Server-Class Processors

Arm has been moving from its foundational base in mobile into the data center, with server-class processors under the name Neoverse. Initially, there was the Neoverse-N1 processor. In addition, some hyperscale companies have been designing their own server-class processors, most notably Amazon AWS with its Graviton and Graviton 2 processors (based on the Neoverse). Not to mention Fujitsu taking the crown with the world's fastest supercomputer build on Arm architecture. Arm also recently announced the next generation of its instruction set (v9) which I will cover in tomorrow's Breakfast Bytes post.

For details on these, see my posts:

• Xcelium Is 50% Faster on AWS's New Arm Server Chip
• EDA on AWS Graviton
• Arm Goes for It
• Arm TechCon: Get Ready for the NEOVERSE
• Taking Arm Neoverse into 3D with Digital Full Flow
• The Start of the Arm Era
• Japanese Arm-Powered Supercomputer Takes the TOP500 Crown

Last September, Arm announced the Neoverse-V1 processor and Neoverse-N2 processor. The N2 is the successor to the N1, a general-purpose server-class processor with balanced power/performance characteristics. The V1 is focused just on performance, but obviously uses more power and area to deliver it. Or in Arm's own words:

The Neoverse N2 platform delivers superior per-thread performance, maximum per-socket throughput, and industry-leading performance per watt leading to reduced customer TCO. Stats: 40% IPC increase (vs N1), industry-leading perfomance per watt, targeted and power and space-limited applications.

The Neoverse V1 platform delivers leading per-core performance, vector performance and code longevity with SVE, and SoC designer implementation flexibility. Stats: 50% IPC increase (vs N1), 256bit SVE implementation doubles the floating-point vector execution capability (vs N1) and is now vector-length agnostic.

Cadence has been working with Arm to smooth the implementation of these latest Arm server-class platforms for licensees.

RAKs

To build a successful server-class processor takes more than just licensing the IP from Arm, it takes an optimized design flow. Cadence has been working with Arm in this area for some time, with an optimized digital full flow and verification tools to enable Neoverse-N1 designs to be implemented efficiently in 7nm. Of course, with enough time and effort, a design group might be able to build an optimized flow from a standing start. But that's the point: it takes time and effort, and a leading-edge Arm platform on a leading-edge process node is typically short of both.

Today, Cadence announced that it has optimized its RTL to GDS II full flow and delivered rapid adoption kits (RAKs) for both 5nm and 7nm for Arm's Neoverse-V1 and Neoverse-N2 processors to allow customers to get their designs to market faster. Also, the Cadence Verification Suite allows Neoverse-V1 and Neoverse-N2 processor users to improve verification throughput and demonstrate SBSA compliance faster.

For details on the digital full flow, especially in the context of implementing Arm processors, see my posts:

• Digital Full Flow for 5/7nm
• Arm/Cadence on Implementing Advanced Microprocessors in Advanced Processes
• Best of CadenceLIVE 2020: Hyperscale Data Centers

For recent posts on the Verification Suite, see:

• Computational Logistics
• Paul Cunningham's DVCon Keynote: Verification Throughput = Engines × Logistics

SBSA is the Server Base System Architecture, a hardware system architecture for 64-bit Arm servers. Hardware that is compliant with SBSA will "Just Work" with standard operating systems and hypervisors. SBSA is part of Arm's SystemReady (SR) program:

Arm SystemReady SR (formerly Arm ServerReady) provides a solution for servers that Just Works, allowing partners to deploy Arm servers with confidence. The program is based on industry standards and the Server Base System Architecture (SBSA) and Server Base Boot Requirement (SBBR) supplements, alongside the Arm Server Architectural Compliance Suite (ACS). Arm SystemReady SR ensures that Arm-based servers work out of the box, offering seamless interoperability with standard operating systems, hypervisors, and software.

In the hyperscale data center post linked above, I wrote about a 4GHz Arm implementation using Cadence's Digital Full Flow, based on a presentation by Arm at CadenceLIVE Europe last year. The processor was described as "the largest A-class processor". In fact, it turns out it was the Neoverse-V1 processor, successfully implemented at 4GHz in 5nm using Cadence's digital full flow.

Here's Chris Bergey again:

By working with Cadence to optimize its digital full flow and its Verification Suite for designs that modern infrastructure solutions demand, our hyperscaler customers can quickly develop Neoverse-based products while keeping cost and power consumption in check.

30 Years of Arm

See the 30 years history of Arm in just over 2 minutes, from its days in the barn outside Cambridge to today's server-class processors:

Learn More

See the Arm-based SoC Implementation page on the Cadence website. Or the RAKs for Arm-Based Designs page.

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