CDNDrive Automotive Solutions: the Rear Wheels

Yesterday was the first of two posts about Cadence Automotive Solutions. Today we go down into the details a bit more. However, there are so many details that this will be more of a map of the landscape so you get an idea of the breadth of our technology. Each item could have a blog post all of its own, and in many cases I have already covered the topic in detail.

Silicon IP

Cadence has a broad IP portfolio, some of which is applicable to automotive as well as other markets, although it needs extended characterization for automotive temperature ranges and, perhaps, lifetimes. See my post Cadence Automotive IP Solutions. One key piece of IP is automotive ethernet. See my post Ethernet: Coming Soon to a Car Near You.

Here I will focus on the Tensilica processor IP. General purpose microprocessors are far too slow and power hungry to handle all the processing coming from perhaps a dozen or more sensors (camera, radar, lidar, ultrasonic). The only possible approaches are to build completely hand-crafted logic, or use a specialized processor that is optimized for the particular function. There are a range of processors, some great for audio but with nowhere near enough power for video, for example.

I'll just summarize the Vision C5 DSP which is a dedicated neural network processor, which can also be clustered into multiprocessor systems. It achieves 1 TMAC/s in 16nm in less than 1mm2. It can run all neural network layers, convolutional and later. For high performance, it has a 1024-bit wide memory interface. For full details see my post Vision C5 Dedicated Neural Network Processor. There is a tool flow that compiles neural networks from all the popular environments such as TensorFlow or Caffe.

The lower powered Tensilica processors also have their niches, for vision or audio processing. High performance when you need it, even lower power when you don't.

Functional Safety

Functional safety is something that could fill dozens of blog posts. Just in case you don't know, a FIT is a failure-in-time, 1 FIT is one failure per billion hour of operation. A car should have <10 FITS. However, a silicon process has more like 500 FITS. So you immediately see the problem: how do you make a reliable car out of unreliable components. It is a similar problem to the one cloud datacenters have, where servers and storage drives fail all the time, the overall datacenter must be rock-solid. A good summary of the main functional safety process is in my post Make Sure Your Car Doesn't Break Too Often...When It Does, Make Sure You Catch It.

If you have been in IC design for decades, back in the days of gate-level simulation, you may remember fault simulation from the days before scan-test and built-in-self-test (BIST). We used functional vectors to create the manufacturing test, but we still needed to make sure it was good enough. For this we used fault-simulation, which (oversimplifying) made sure that any faulty gate would be detected during manufacturing. The same basic approach, but taken to a new level, is used for automotive: make a list of all the things that might go wrong, and then make sure not that it would be detected, but that it would be handled appropriately (maybe correcting it in the case of a memory read, turning on a warning light for something not too serious, or dropping an autonomous car back into an emergency safe mode). It is easy to get a little confused in this area, since "normal operation" includes things like crashing and making sure the airbags deploy, even though most of us hope never to operate our cars that way.

The acronym in this space is FMEDA, which stands for Failure Modes, Effects, and Diagnostic Analysis. This requires a whole process starting from safety requirements and FIT rates, all the way down to things like options in Innovus physical design to create safety islands, and add redundant vias. That's quite a range of areas of concern.

Reliability

Reliability in semiconductor has a special meaning, and doesn't mean the same as safety. It is concerned with aging of integrated circuits. This is especially acute with automotive since aging is made worse at higher temperatures, and those transistors have to last for a long time, 15-20 years. The target defect rate is very high, 0ppm. It turns out that up to 95% of all field failures are due to the analog or mixed-signal portion of products. This post is long enough already, but like on those cooking shows, I have one I made earlier. Look at Legato: Smooth Reliability for Automobiles. Find out what a bathtub curve is, if you don't already know.

Summary

It goes without saying, that this somewhat random seeming laundry list is in additional to the complete Cadence tool flow, these are the things that are added to a normal tool flow to make it ready to drive off the lot and start an automotive SoC design. It is by no means a complete list.

• Broad-based partner for automotive system design enablement
• Strong ADAS offering for high-performance, low-power SoCs
  • Tensilica – the common acceleration platform for ADAS
  • Dedicated neural network processor core incl. NN compiler
  • ADAS Rapid Prototyping system incl. quad-core Tensilica Vision P6
• Scalable Infotainment solution based on Tensilica HiFi
  • Tensilica Processor ISO 26262 Compliance
  • Certified ASIL B(D) Ready as SEooC
• ISO 26262 Processor Safety Kit
• Validated design flows, tools and IP for ISO 26262 compliant product design and certification
• Legato: Design-for-Reliability solution

Sign up for Sunday Brunch, the weekly Breakfast Bytes email