CadenceLIVE Europe 2022

CadenceLIVE Europe took place on Monday and Tuesday at the start of Thanksgiving week in Munich, Germany. It was in-person for the first time in three years. There were about 550 people there, maximum capacity. As in the past, the first day starts at lunchtime on Monday to give people time to fly in from other parts of Europe. Then, CadenceLIVE kicked off with keynotes.

Tom Beckley, Cadence

Tom Beckley opened up the conference with his keynote. Tom has a very wide portfolio of products, including PCB, packaging, RF, system analysis, custom and analog design, and more. He started by looking at the challenges and opportunities facing the semiconductor industry as we approach the start of 2023:

• Moore's Law is not dead, and "more than Moore" is perhaps the hottest area in semiconductors right now
• There is a global shortage of semiconductors, especially in automotive
• Increasing electrification of automotive, aerospace and defense, consumer, and industrial markets
• Systems companies are building their own silicon
• There is a worldwide scarcity of engineering talent
• Everyone's got a CHIPS act: foundry capital investment plus government subsidies to improve supply chain resilience
• AI innovation
• The semiconductor market is forecast to grow 50% in the next decade
• GlobalFoundries is out of capacity through the end of 2023

Tom moved on to give a brief tutorial on the October 7th announcement by The Department of Commerce’s Bureau of Industry and Security (which apparently was not discussed with the Department of Defense and caught them by surprise).

Most of the rest of Tom's talk was about various recent product announcements. Since I covered all of those when we made the announcements, I won't repeat everything here.

Tom wrapped up by teasing everyone with a preview of some results from future AI enablement in PCB and IC Packaging that we will be announcing in 2023. For example, the above PCB took 59 hours to route after a manual placement. Using AI-driven placement and routing, the board was routed in 20 minutes and had 16% better wirelength. When we officially announce this capability next year, I will cover it here on Breakfast Bytes.

Oliver Wolst, Bosch

The industry keynote was given by Dr. Oliver Wolst of Bosch Semiconductors. He started out with a few slides on Bosch's operations all over the world. They have over 36 manufacturing sites in 17 countries and have capabilities for semiconductor design of CMOS, RF-CMOS, analog, mixed-signal, MEMS, and power.

He was especially pleased that in 2017, Bosch had decided to build a 300mm wafer fab in Dresden, three years before the start of the semiconductor shortage. He said that they often manufacture the same part at foundries and in-house, which has helped during the shortage by giving them flexibility. He wrapped up that section:

You’ve made it through the advertising block. So let’s talk about change.

He discussed how there is going to be a change in architecture to a service-oriented architecture...but today all in-vehicle communication is signal-based.

All automotive OEMs will introduce new digital business models…about ten years after Tesla did it.

Only a centralized architecture can hold the software complexity, and most of the OEMs (car companies) have developed such an architecture to be introduced in 2026+, but there are issues:

All these architectures across all brands are much too costly. Also, scalability has not been achieved. Why has that failed?

His view is that there are two reasons. The first is technology consistency of functional blocks for functions that are distributed, and the second is there is a collaboration model between different companies that is new and has yet to grow. In the past, systems were designed by the tier-1s (like Bosch). Now we are moving to what he calls IDM+, a semiconductor maker with a semiconductor business but also a system business.

There are new requirements for hardware-software co-design. Bosch is convinced that they need to build a model of the entire hardware for running the full software stack. But they need to avoid adding additional compute at every level, or the whole stack will be anything but lean.

Of course, the foundation for this type of development is the dynamic duo, Palladium Zx and Protium Xx (where x is 1 or 2). One example took two months to bring up in Protium, then a few more months to add SpeedBridge, and they could communicate with real Ethernet test equipment.

Everyone is unhappy with the current state of central computing. There is lots of complaining and the integration costs are spinning out of control. Despite this, all the OEMs are going to have a central architecture in 2025 to 2026. By 2029, about half the vehicles on the planet will have a centralized architecture.

Other challenges are that there is not enough PCB space for all the chips. The power consumption is completely unacceptable. Efficient scalability is not there at all. Not to mention time-to-market.

In HPC, the trend is to chiplets (see lots of Breakfast Bytes posts on just this topic). This might be a solution to these issues. However, the R&D cost is much too high for the automotive market to shoulder on its own.

Oliver had a chiplet wishlist. Reading between the lines, the automotive industry is betting on a supply of COTS chiplets developed for other purposes but that they can then reuse in automotive. This requires a change in approach:

A market of multiple suppliers contributing chiplets, rather than a captive business model doing it all in one stack. Need system-level planning and top-down thinking.

But it is a frightening number of chiplets, so we are working on how to reduce these numbers. How to scale with the least possible number of chiplets. And how to use non-automotive chiplets, too.

Finally, he came to what he called "the most important slide of the day" about the Open SoC Ecosystem for Automotive (see above).

Today we see two companies addressing this in its entirety. Must have synergy with non-automotive market since the automotive market alone is too small to recover the investment. For level 3 and level 4 driving, we do not see any components that are meeting the requirements since the dataflow in these SoCs is not what is needed. So that the task is not covered. In addition, these companies will not offer a scalable portfolio since it is an additional cost that can’t be borne.

I'm guessing he is referring to Qualcomm and NVIDIA since they are the only companies addressing the whole stack. Of course, Tesla is doing its own stack, but that doesn't help other OEMs.

The chiplet is not just the technology, it is a trend that would allow new kinds of cooperative business models, synergies that are definitely required.

Captive business models, that was yesterday. That is how Bosch will proceed going forward.

Technical Sessions

The rest of the day (and the following day) were taken up by multiple parallel tracks:

• Automotive and IP Solutions
• Digital Design and Signoff
• Verification
• PCB and Multiphysics Systems
• RF, RF Systems, and Packaging
• Cloud
• Custom and Analog Design
• Mixed Signal Design
• Academic

I attended a selection of these sessions, which I will write blog posts about during the rest of the year.

A Fireside Chat

Monday evening finished with a social/networking hour in the expo hall, followed by dinner in the big ballroom where the keynotes had taken place. In between, there was a "fireside chat" in which Rebecca Dobson, corporate VP of WFO for Europe, interviewed some guy called Paul McLellan. We talked about trends in the semiconductor industry, most notably automotive, since Robert Schweiger and I had a new automotive book that we were giving away. For details on the book, see my post, Books: Hyperscale and Automotive.

 

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