CadenceLIVE India: Best Paper Awards

CadenceLIVE India gives out a best paper award on each track to the presentation that the attendees vote as the best. Over at The India Circuit Blog, Sangram Jena provides a table with all the winners. I took a look at three of the winners in three different areas:

• Front-End Design track: Efficient Handling of Super Under Drive Corner with Genus iSpatial at Lower Tech Nodes by Shubham Gupta of Samsung
• Custom Implementation track: CLE (Concurrent Layout Editing), a New “Advanced” Methodology for the Next Generation of MSoT Smart Power (BCD) Design by Mona Joshi and Sakshi Singh of STMicroelectronics
• Emulation and Prototyping track: Improving Firmware Validation Productivity and Debug Efficiency Using Palladium Z1 Platform and Indago Debug Analyzer by Ponnam Lakhsmanan of Analog Devices

If you registered for CadenceLIVE India, then you can access the presentation replays for at least the next few weeks by clicking on "watch now" here. Then click on "theater", and then on the appropriate track, and then on the paper you want to watch.

Super Underdrive Corner

Samsung's Subham Gupta reported on a project to design a very low powered SoC that operated at sub-threshold voltages. His presentation was titled Efficient Handling of Super Under Drive Corner with Genus iSpatial at Lower Tech Nodes.

There are many challenges to doing operating at very low voltage, the biggest being the enormous amount of variation in this corner, and the difficulty in guaranteeing to make timing. Subham used Genus for synthesis, and Innovus for implementation, and the iSpatial technology that links the two. For more details on iSpatial see my post Digital Full Flow for 5/7nm.

The targets were:

• High-frequency target at super underdrive (SUD) corner
• High sigma (for process variation) and guard band (for voltage and temperature) at SUD
• SLVT cell usage should be less than 3%
• Optimal area

He started by making SLVT cells off-limits, but that turned out to be impossible to close at the desired frequency. But when SLVT cells were allowed, Genus used too many of them and although the design would close, now the leakage was too high. Typically, very low voltage applications like this spend a lot of their time in some sort of standby mode where they are not doing much, and as a result, leakage is very important and can count for most of the power dissipation. By tweaking the parameters they managed to get the use of SLVT cells down. The graph below shows the three possibilities. The blue bars show the frequency coming up as various approaches were tried. The red bars show the percentage of SLVT cells used.

Concurrent Layout Editing

STM's Mona Joshi and Sakshi Singh presented CLE (Concurrent Layout Editing), a New “Advanced” Methodology for the Next Generation of MSoT Smart Power (BCD) Design. BCD is a technology originally invented by ST over thirty years ago. B stands for Bipolar, C stands for CMOS, and D stands for DMOS. All combined in a single process, largely used for industrial and other power applications.

Mona described what ST calls the "Analog on Top" BCD flow, based on Virtuoso. Concurrent Layout Editing (CLE) is what it sounds like, multiple people working on a single layout to accomplish a task. To avoid everyone stepping on each other's feet, the design is partitioned. An example is at the top level of the chip, when everything is assembled with blocks from many different designers, and there are thousands of DRC errors. Since it is the end of the project, it is important to get everything fixed as quickly as possible, and that means as many people as possible fixing things concurrently. The design is partitioned into however many engineers are available, and each engineer works on his or her partition, but on a common layout database for the whole top-level. However, each engineer sees all the errors, which is not convenient. ST has an internal tool that partitions things so that each engineer only sees the DRC violations for their partition, and the ones in other partitions are only seen by their respective engineers. So you end up with a flow like this (this example is just partitioning between two engineers, left and right).

Sakshi then took over to describe how they used this approach on a real design. She talked about some of the other areas where this approach can be used, but then went into detail on the above flow, fixing DRC violations and DRM errors in an IP block. She also talked about the future, and the possibility of using other partitions than area-based, such as layer-based, and also how to bring automatic routing into the methodology.

The final number is that using CLE saves about 30% of time, and improved quality. Also, because everyone is working on the same cell-view database, connectivity is maintained.

Improving Firmware Validation

ADI's Ponnam Lakhsmanan presented Improving Firmware Validation Productivity and Debug Efficiency Using Palladium Z1 Platform and Indago Debug Analyzer.

He went into a lot of detail about exactly how they hooked up their test environment (running in simulation) to their device under test (DUT) running in the emulator, and how they avoided having to record all the signals from the emulator.

However, in order not to tie up the emulator, all debugging is done offline with Indago. And finally, the results:

Congratulations to all the winners of the best paper awards, but especially the engineers I featured in this post.

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