CDNLive Boston Overview

CDNLive Boston took place last week. It is really CDNLive East Coast, and there were plenty of people who had come from further afield, such as Florida and North Carolina. I came from California, along with many of the corporate marketing team that run the event.

Keynotes

The day opened with three keynotes. The first was by Daryn Lau, who runs R&D for emulation and FPGA prototyping. He gave his version of what I think of as the standard Cadence corporate keynote. It was not different enough from the version I covered in India to repeat it all, so you can see that in my post CDNLive India Keynote. One little piece of information that Daryn Lau mentioned was the Palladium had a record quarter in Q1, and beat that with another record quarter in Q2. Since Palladium Z1 was only released in December last year, that is a steep ramp.

The second keynote was by Paul Cunningham, who runs R&D for Digital and Signoff. I first met Paul at a Cambridge alumni event. When I asked him what he did, he said something like "It won't mean anything to you, I doubt, but I run a startup doing clock tree synthesis." To his surprise, I knew exactly what that was. He was the CEO of Azuro and Cadence would go on to acquire them in 2011.

Paul gave an interesting history of signoff. When synthesis was first introduced in the early 1990s, almost all capacitance was gate-capacitance, the capacitance due to interconnect was a secondary correction. As a result, synthesis was responsible for the netlist and meeting timing. Physical design just placed the cells and hooked them up, and didn't even consider timing. Then wire capacitance became significant and had to be taken into account during synthesis, this was the era of physical synthesis. When I was pitching Ambit's PKS in that era, I would say that not using physical synthesis was like trying to plan how long a journey to visit some cities in the US would take, without knowing which cities they were. Next, resistance became significant and could no longer be ignored. Since different metal layers have different thicknesses, they also have difference resistance (by the way, sheet resistance is measured in Ω/☐, ohms per square, since it doesn't matter how big the square is, the resistance from one side to the opposite side is constant). So timing analysis needed to take account not just of placement but also the layers used for the routing. Now it has to take account of pretty much everything: metal layers, metal coloring when double-patterned, vias.

The complexity of this has driven Cadence's creation of the new family of implementation tools: there is a single timing engine, a single placement engine, a single extractor, and so on. Coupled with making the tools run on modern massively parallel server farms, this has created a new generation of implementation tools, the ones with "us" at the end.

The third keynote was by Dr William Chappell Director, Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office. I will cover that in more detail in a separate posting.

RFIC Design Using Cadence's Hosted Design Services

Sticking with the government, the next session I attended was by the Naval Research Laboratory (NRL), part of the Office of Naval Research (ONR) by Jack Holloway, who is a research engineer there, working towards a PhD at MIT, but also assigned to NRL. Since he is in the military, he is also Captain Holloway (I'm not sure what happens when he gets his PhD, Captain Doctor Holloway? Doctor Captain Holloway?). He talked about a project called SPEAR and its challenges. SPEAR stands for Signal Processing Electronc Attack RFIC. He couldn't go into the details since it is secret, but it is a very high-performance radar of some sort, and they are designing everything from antennas, high-speed PCB board, the RFIC, a DSP, and a GUI on the backend. It is a large program with lots of different specialties involved. The RFIC chip is high-frequency mixed-signal with RF in and data out.

Their basic approach is to do the advanced stuff in house and contract out the more "pedestrian" parts of the design. One challenge is this type of project is the contracting. The layout engineers work for one of the subcontractors and it can take as much as a year to get that sort of contract in place. Not exactly agile.

They are using the GLOBALFOUNDRIES BiCMOS BHP process, which meets the ITAR requirements (I guess it will be manufactured in New York, not Singapore), provides the right balance between performance and cost, and there are regular MOSIS MPW runs.

They started using a Red Hat-based box with Virtuoso ADE XL and QRC. But NRL didn't have enough infrastructure for a project like this, not enough servers and not enough tools, and complex distribution: circuit design was being done by three engineers in two different organizations, layout by two engineers from a different organization, and all needed to be under ITAR access controls.

So they approached Cadence about a VCAD-hosted design solution. It turned out to be a great choice. They could get IT support through Cadence, ITAR compliance, hardware VPN, a US-based server, support provided by US persons. It was also flexible in that they could get some number of temporary keys for tools they only needed for a few hours. All the team members, whichever company they worked for, were sharing a common database with live reporting.

A military project like this with all the ITAR rules is not exactly typical, with some strict requirements, but VCAD-hosted design seemed to be able to provide everything.

Comprehensive Extraction Tool for Parasitics and EMIR for TSMC 10nm

This presentation was by Brandon Bautz of Cadence and Tom Quan who runs OIP at TSMC. I don't think Tom was actually in Boston, at least I never saw him, and the presentation was by Brandon.

FinFETs present some new challenges for extraction, in all three "ends" of the line:

• FEOL (FinFET transistors)
  • Dominated by fringe 3D capacitance from gate fins
  • Thickness of gate introduces new capacitances
• MEOL (2 layers of local interconnect)
  
  • Explosions of resistance requiring better handling to expedite post-layout simulation
  • More capacitances to M0/V0 contacts
• BEOL (metal stack with multi-patterning)
  
  • No more uncertainty due to mask shift (self-aligned)
  • Required methodology change to full coloring
  • Performance improvement reduces lateral Xcap

TSMC had some specific requirements for certification:

So, in summary, the reasons why designers use Quantus for FinFET designs are:

• Accuracy for FinFET designs (certified by TSMC)
• Fastest single-corner and multi-corner extraction runtimes
• Tight integration with Innovus and Virtuoso solutions (faster ECO iteration)
• Tight integration with Tempus timing signoff (3X faster signoff, accurate incremental extraction)
• Only extraction tool certified at TSMC with Voltus-Fi solution for EMIR support

SI and PI Panel Session

The last session I attended was a double session, a panel session with five industry experts, moderated by me. I'll write a whole post about the panel soon. But to whet your appetite, the panel consisted of:

• Istvan Novak – Senior Principal Engineer at Oracle
• Kevin Roselle – Senior Staff Engineer at Qualcomm
• Dale Becker – Chief Electronics Packaging Engineer at IBM
• Stephen Scearce – Senior Manager of High-Speed Design at Cisco
• Ken Willis – Product Engineering Director of High-Speed Analysis Products at Cadence

That's well over a century of experience when added together.

Then the band started, the bar opened, and food was served.

Softbank and ARM

Nothing to do with CDNLive Boston, but in case you didn't see it since it happened on Labor Day in the US, Softbank completed its acquisition of ARM Holdings. ARM is now a Japanese company. ARM will be delisted from the LSE September 6th.

Next: SiFive: a RISC-V Fabless Semiconductor Company

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