Breakfast Bytes Blogs

This morning, Cadence announced Cerebrus Intelligent Chip Explorer, a machine learning (ML)-based tool that automates and scales digital chip design. If you think about what a designer does with traditional EDA tools, a lot of it is running some tool, analyzing the results to look for anomalies or places for improvement, tweaking a few parameters, and then running the tool again. The best designers do this a lot better than less experienced designers. One reason is that they have seen more designs in a longer career. But another is that they probably worked on the last version of the chip, or on other similar chips at the same company. Less experienced designers, a new hire being the most extreme case, take significant time to get experienced with the design they are working on, and the library and IP being used.

Traditionally, EDA tools have not made any attempt to do any of this automatically. A typical tool reads in the design representation (SystemVerilog, say) and starts over from scratch, even though the SystemVerilog might be identical to last time the tool was run, or perhaps in a more extreme case, only 95% the same. The libraries and IP will be the same, or almost.

It makes very little sense in the cloud and massive data center era to use designers, especially the most experienced ones, to do things where we could substitute computer power—even if it takes a lot of computer power. Another challenge, a nice one to have, is that the semiconductor industry is booming with strong growth in many areas such as 5G, autonomous driving and ADAS, hyperscale compute, industrial IoT, and more. For more background on this, see my blog posts The Five Waves: AI, 5G, Cars, Clouds, IoT and its second part Four More Waves: 5G, Cars, Clouds, IoT. The result of this renaissance in the semiconductor industry is that, even more than before, engineers are overloaded and under pressure to produce next-generation chips even faster, despite often being on a more advanced and so more challenging semiconductor process node.

Help is on the way for digital design in the form of Cerebrus Intelligent Chip Explorer.

Cerebrus replaces humans-in-the-loop by using a lot of computer power, in a way analogous to how synthesis replaced manual entry of schematics by using a lot more computer power. That was a big discontinuity, and the use of machine learning is another, different from the routing incremental improvement that all EDA tools have to make every year to keep up with the growing complexity of designs.

Cerebrus uses unique reinforcement ML to deliver up to 10X productivity improvement, and 20% improvement in PPA (power, performance, and area/cost). It works with computing resources of both on-premises (on-prem) data centers or cloud providers such as AWS. It drives the productivity curve to the left, lowering the amount of engineering effort, and also up, improving PPA. it is especially appropriate for the most advanced nodes where manual approaches are often ineffective due to the need to handle things like high-resistance interconnect, IR-droop, very complex design rules, and other factors that make completing and signing off on a modern design the biggest game of whack-a-mole ever. Cerebrus adds reinforcement learning and a knowledge graph to the digital full flow of Genus synthesis, Innovus physical design, and Tempus static timing signoff.

One example is a 5nm mobile CPU. There had been extensive manual flow development. But Cerberus converged on an improved flow in just 10 days. Performance was up 14% to 420MHz. Leakage power was down 7% to 26mW. Total power (dynamic and static) was 3% better at 62mW. Density was up 5%. Cerebrus is like having the superman of designers added to your team.

Another example is using Cerebrus's power for automated floorplan exploration using the mixed placer. For more on the mixed placer before adding ML, see my post Innovus Mixed Placer. This was a 12nm design where the design team wanted 2GHz performance. Cerebrus optimized the floorplan and implementation flow concurrently, improving the performance by 200MHz, reducing the number of paths failing timing by 83%, and reducing leakage power by 17%.

Cerebrus doesn't just tune the flow and adjust parameters, it can also do more extensive exploration. In this example, Cerebrus considered various different floorplans, adjusted all the macro positions with the mixed-placer, and made other adjustments to the flow. This resulted in a 200MHz improvement in clock speed, an 83% reduction in the number of paths with negative slack, and a 17% reduction in leakage power.

Results at Customers

Two of the customers that the Cerebrus team has been working with before the product was announced today are Renesas and Samsung Foundry.

In our press release, Satoshi Sibatani, director at the Shared R&D EDA Division at Renasas, says Cerebrus improved design performance by more than 10% and:

Following this success, the new approach will be adopted in the development of our latest design projects.

Samsung Foundry has been using Cerebrus as part of DTCO (Design Technology Co-Optimization) for assessing the impact of process features on PPA. For more details on what DTCO means, see my post about Lars Liebmann's presentation IEDM: Automating DTCO for 3nm. Samyung Kim, VP of Design Technology reported Samsung Foundry's results:

We’ve observed more than an 8% power reduction on some of our most critical blocks in just a few days versus many months of manual effort. In addition, we are using Cerebrus for automated floorplan power distribution network sizing, which has resulted in more than 50% better final design timing.

Okay, if you are getting 50% improvement in timing, you weren't trying very hard to begin with. And in DTCO that is the point, you want to try lots of things without putting a lot of effort into each one. Cerebrus steps in and tells you the implications of some DTCO thing like, say, buried power rail, without needing a huge team of people for each alternative.

Summary

Learn More

See the Cerebrus Product Page.

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.