New Cerebrus Webinar This Month

Cerebrus is Cadence's new machine learning-enabled digital design environment. When we announced the product in July, I covered it in my post Cerebrus: The Future of Intelligent Chip Design.

Coming up on September 16 at 10:00am PDT is a new webinar How to Improve Your Chip Design Performance and Productivity Using Machine Learning.

New applications and technology are driving demand for even more compute power and functionality in the devices we use every day. This has resulted in the semiconductor industry experiencing strong growth based on technology like 5G, autonomous driving, hyperscale compute, industrial IoT, and many others. System-on-chip (SoC) designs are quickly migrating to new process nodes and rapidly growing in size and complexity. Unfortunately, engineering teams are becoming overloaded and cannot keep up with ever-increasing design starts. 

Machine learning combined with distributed computing offers new capabilities to automate and scale RTL-to-GDS chip implementation flows, enabling design teams to support more, and increasingly complex, SoC projects. During this webinar, we will explain key technologies behind the new Cadence Cerebrus Intelligent Chip Explorer and the RTL-to-signoff implementation flow to show how they can help you achieve up to 10X productivity and 20% PPA improvements for implementation.  

The semiconductor industry is growing fast, driven largely by the increased silicon content in pretty much every product: 5G, automotive, hyperscale data centers, industrial IoT, and more. This increase in both the number of new designs and their complexity is putting design teams under a lot of pressure to deliver. Next-generation chips need to be produced faster and smarter. By adding deep learning to the digital full flow, better results can be achieved without requiring months of manual iteration.

The diagram on the left shows the traditional manual flow, pre-Cerebrus. On the right is the Cerebrus flow, with a lot of the interaction and exploration automated intelligently using machine learning.

The webinar will go into details of how Cerebrus works and how to get the best results from the product. Talking of results, below is one example. Instead of requiring months of manual work, This is a 3.5GHz CPU design in 5nm and Cerebrus allowed one engineer to complete the physical design and make a significant improvement to operating frequency, leakage power, and area. In particular, an improvement of 14% in its performance.

During the webinar, you will also see how Cerebrus can be used for automatic floorplan exploration, in tandem with Innovus's mixed placer to find the best macro placement, and then create the power mesh, for a 4nm design, improving the performance of one of the blocks by 67%.

Renasas and Samsung

Two of the early customers of Cerebrus were Renesas and Samsung Foundry. Here' are two Designed with Cadence video showing some of their' experience.

Learn More

See the webinar product page, including a link for registration. Once again, it is Thursday September 16 at 10:00am PDT.

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