DAC 2020: Chips in 2030

In 2015, soon after I rejoined Cadence, I went to IEDM, the International Electron Devices Meeting. That year it was in Washington DC. I paid for most of the trip myself since I'd already booked the flights and hotels months in advance to get good prices or use hotel points...and of course I hadn't gone through the Cadence travel service. But I remember two big things from IEDM that year that are relevant to this post nearly five years later.

The first was that one of the plenary presentations (what other places call keynotes) was by Greg Yeric of Arm. He titled it Moore's Law at 50: Are We Planning for Retirement? (short answer: no, but you can read my post about the whole presentation at the link).

The second was during the short courses on the Sunday of IEDM about IEDM Examines Options for 5nm...Academics and Industry Examine the Options. In the morning, academics presented all sorts of esoteric devices that may or may not be attractive. In the afternoon, two teams from IBM basically said that none of that would happen. It takes 10-15 years for a technology to go from the lab to volume manufacturing. Therefore 5nm would be some sort of FinFET, or possibly some gate all around (GAA) technology which is very similar to FinFET. Then interconnect got the same treatment. We have to improve what we have and not do something radical. So 5nm will be copper, perhaps with some additional metals might creep in. Well, those IBM guys were pretty accurate. 5nm is FinFET with copper interconnect, perhaps with little bits of cobalt. But the big takeaway for me was not exactly how 5nm might look but the message that if you look ahead ten years, then we already have to have the technology we will end up with well past the research stage.

Greg Yeric

Well, both these pieces of history came together at a DAC SKY Talk by Greg Yeric called Design and Manufacturing in 2030. Greg talked about so many different facets of what might change in the next decade that I'm not going to attempt to be comprehensive. I'm just going to pick and choose three or four areas that Greg discussed and focus on them.

I said in my preview to DAC that I'd already seen a shorter earlier version of some of this material. Indeed, Greg opened with his "Moore's Law" graph that eventually he reveals is not Moore's Law at all but the cost of a lithographic stepper over time. I showed that in my post Arm TechCon: A Look at 2020 and 2030.

Greg was looking at PPA as a structure for his talk, and started with A for area. Area is also a surrogate for cost, and a lot of cost is tied up in lithography. EUV finally seems to be working and costs about $120M per machine. The next-generation, high numerical aperture (NA) EUV will be much more expensive. Although, as Greg pointed out, it is currently forecast below trend line. "It's a bargain." But I will caution that if prediction is error-prone, predictions about EUV have historically been especially error-prone. Remember what year we were meant to have EUV insertion?

But by 2030, we're looking at spending more than $1B per tool to do what we need in 2030.

These top-down approaches are just too expensive and challenging, we need bottom-up and some sort of self-assembly, which I've also heard described as "lithography in a bottle". But Greg's focus was not on the existing work on making grids and lattices, but self-assembly through DNA (yes, the biological DNA, this is not some weird lithography acronym you don't know).

Here are some of the DNA Origami Tiles Rothman made in 2006, smiley faces, stars, and to give you a perspective on dimension, our upcoming 3nm node will be lucky to put two gate lines down where he's been doing smiley faces and stars for over a decade.

Just sprinkling these on the wafer won't do much good, but work by Lulu Qian and others allows for fractal assembly.

They took a test-tube that would build one of Rothman's tiles, ordered three more, programmed them to only assemble along the edges, then replicated that.
...

By the time they were done they had the world's smallest Mona Lisa, about 700nm across. Now our high-end $255M high-NA EUV tools won't be able to make that. Who did make that were a couple of post-docs, a spreadsheet, and $20 of DNA. They get about a billion copies per test tube, so you're looking at a 20¢ Mona Lisa.

Another reason Greg is bullish on some form of DNA self-assembly is that "it doesn't need us". By "us", he means the semiconductor industry.

We spend a lot of money on research in semiconductor but we are only number 2. Number 1 is healthcare. And in the healthcare industry, they are currently curing cancer in mice using DNA origami. So technologies like this that can benefit more than one industry...we should be paying attention to it.

Next Greg moved onto new materials. I won't go into detail but the big challenge with most of these materials is that they don't look anything like CMOS. But we can't get where we need to go just with CMOS.

But there is a chicken-and-egg problem:

We can't expect the EDA industry to develop a flow for every new technology that comes along. This is a problem I expect to see more and more when we see these fundamentallly different technologies

This is part of a well-recognized issue that sometimes goes under the name "lab to fab". There is money for governments and universities to do research and innovation. Once an industrial sector settles on a technology then the private sector will invest. Look at EDA or the foundries or the manufacturing equipment. But in between, there is a gap. As I said at the start of this post, it takes ten years to go from research to volume production, from lab to fab in this terminology. But it takes a lot of money, so much that there has to be broad agreement as to which horse to bet on. Or horses, but very few of them. It is simply not possible for a foundry, for example, to ramp up twenty processes based on different materials to full volume production, and then see which ones are interesting. Plus, of course, the EDA industry needs to pick, and they need to pick the same answers as the foundries and the system companies.

The best example of this was 300mm wafer manufacturing. Any one equipment manufacturer can't move unless a whole process is available, and if the foundries agree to adopt, and if wafer blanks are available, and so on. This change didn't really even involve EDA so it was relatively simple. Imagine the investment required if we move to one of the technologies Greg discussed that requires cryogenic cooling, probably different manufacturing equipment, certainly a different process. Plus it is built on induction, so standard cells don't work. And wires are superconducting so they don't do fanout. And so on. That would require a whole new manufacturing flow and a whole new EDA flow, with new IP, and probably a whole load of other things (cryogenic test labs for a start).

Greg's wrapup:

I personally think it is an exciting time, this period from now to 2030, because we will have viable new beyond-CMOS options. Those of us in the EDA and manufacturing fields are going to have to get together and figure this out in terms of what can make the jump across this lab to fab gap.

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