Generic and Open PDKs

One challenge that educators and researchers face is that they typically have no access to real PDKs from the foundries, but PDKs are required to do design, even if there is no plan to actually manufacture the design.

PDK stands for process design kit. In the distant past, a process technology would be transferred to designers and EDA companies in the form of a design rule document (on paper) and a SPICE model. That was enough to do layout and simulate it, but as processes got more complex, it was not scalable to transfer all the rules on paper. Instead, it all needed to be encapsulated in some sort of file, and so the PDK was born.

Cadence GPDK

In his blog post, Cadence Advanced Node GPDK v1.1 Released, Anton Klotz of the Cadence Academic Network announced the latest Cadence generic PDK for advanced node, meaning FinFET and multipatterning. As he says:

For academic users, GPDK has the pleasant side effect that these PDKs can be used for education, with no extra NDAs to be signed. The designs are non-manufacturable, but the device models, technology rules and PCells are close enough to their manufacturable counterparts from industry-grade PDKs, so that the electrical effects and design flows are basically the same.

This PDK has been used by students and professors to understand and model the new challenges that are present in the design for advanced nodes. As an example, FinFET transistors have only discrete fin width, many more parasitic elements needs to be taken into account, multipatterning requires new layout styles with avoidance of loop violation, where the shapes cannot be decomposed to two different masks. All these effects could be reproduced with the initial version of the Advanced Nodes GPDK. This PDK also supports features like parasitics extraction, support for mixed-signal design, interactive highlighting of potential electromigration violations (EAD), which are becoming increasingly important in advanced nodes, interactive DRC, DFM fill, support of chaining and folding for stacked devices and more.

Skywater Open Source PDK

Cadence is not the only company in the PDK game. 

The SkyWater Open Source PDK is a collaboration between Google and SkyWater Technology Foundry to provide a fully open source Process Design Kit and related resources, which can be used to create manufacturable designs at SkyWater’s facility.

As of May 2020, this repository is targeting the SKY130 process node. If the SKY130 process node release is successful then in the future more advanced technology nodes may become available.

You can access the Skywater PDK on Github. By the way, if you don't recognize Skywater, it was Cypress Foundry Solutions until it was spun out by private equity. The particular process supported by this PDK, SKY130, is a mature 180nm-130nm hybrid technology originally developed internally by Cypress Semiconductor before being made accessible to general industry. SkyWater and Google’s collaboration is now making this technology accessible to anyone.

But, there is more. Through a collaboration between eFabless, Google, and Skywater, designs can be manufactured. For free! There is a multi-project wafer program, with 40 design slots on each wafer, so this can't be used for volume production, just for prototypes. As it says in the press release announcing the program:

SkyWater Technology, the trusted technology realization partner, and Efabless, a crowdsourcing design platform for custom silicon, today announced design submissions are now being accepted for a series of Google-sponsored open source Multi-Project Wafer (MPW) shuttles that will run at SkyWater. Through a partnership between Google, SkyWater and Efabless, open source designs selected by the program will be fabricated at no cost to the designers. The MPW program is enabled by the first foundry-supported open source process design kit (PDK) for 130 nm mixed-signal CMOS technologies (SKY130 process). The initiative will enable a complete open source manufacturing supply chain for custom application specific integrated circuits (ASICs) and has been discussed in a series of talks produced by the FOSSi (Free and Open Source Silicon) Foundation including presentations by Google and Efabless.

More than 60 percent of projects on the first run of a Google-sponsored shuttle program managed by Efabless with Skywater’s 130nm open-source PDK are from first-time chip designers. This is the closest thing to open source semiconductor manufacturing.

OpenROAD

I wrote about OpenROAD when it was first announced in 2018. See my post ERI: OpenROAD. I then covered it in more detail in my post OpenROAD: Open-Source EDA from RTL to GDSII. The on paragraph summary is:

OpenROAD is a DARPA program to attempt to build a no-human-in-the-loop EDA flow, using only open-source software. The goal is to go from RTL to GDSII fully automatically. In a leading-edge process node. With zero DRC errors. In less than 24 hours.

A lot of progress has been made, which I wrote about in Breakfast Bytes Update: DATE, OpenROAD, Starlink.

But this post is about PDKs, and OpenROAD has released a 7nm PDK to Github known as the ASAP7 7nm ASAP Predictive PDK. It is available to anyone under an open-source license. The ASAP 7nm Predictive PDK was developed at ASU in collaboration with Arm Research. There are 7.5 track and 6 track standard cell libraries.

For a lot more detail, see the two papers:

L. T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthy, and G. Yeric, “ASAP: A 7-nm finFET predictive process design kit,” Microelectronics Journal, vol. 53, pp. 105-115, Jul. 2016.

V. Vashishtha, M. Vangala and L. T. Clark, "ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper," Proc. ICCAD, pp. 992-998, Nov. 2017.

I am sure there are more generic and open-source PDKs out there, but these are the big ones I know about.

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