3D Heterogeneous Integration (3DHI)

Shakespeare (in Romeo and Juliet) wrote:

What's in a name? That which we call a rose by any other name would smell just as sweet.

The Implication is that names do not matter. Shakespeare was clearly not in marketing, where names are acknowledged to be very important. When I was at VLSI Technology in the early 1980s, we needed a name for what we did: taking in customer designs and manufacturing them. We came up with CSIC for Customer Specific Integrated Circuit. It had the positive of being correct but the negative that it was not obvious how to pronounce it. "sea-sick" didn't have great connotations, and "see-ess-eye-see" was a mouthful. Out of nowhere, it seemed, came ASIC, for Applications Specific Integrated Circuit. This had the opposite tradeoff. It was inaccurate since the designs were unique to a customer, not an application, but everyone pronounced it A-sick without any prompting. The name seemed to catch on, and so we switched. Designs like that are often still called ASICs today, over forty years later (and they are still specific to a customer, not an application).

Over the last decade, but mostly in the last five years or so, there have been various attempts to name what is going on when we put more than one die in a package:

• More than Moore (catchy but covers a lot of other things)
• 2.5D (yes, but that is a subset of this type of design, covering die on an interposer only)
• 3D-IC (I see nothing wrong with this one, except it is unclear if 3D-IC also includes 2.5D IC)
• System-in-Package, or SiP (I like this one since it is accurate and general)
• ...there are also various proprietary names that are clearly no good as the generic name for the whole industry

The latest name, which seems to be getting traction, is "heterogeneous integration" or "3D heterogeneous integration." This seems to cover everything from adding some high-bandwidth memory (HBM) stacks to a processor all the way up to what I think is the current winner for complexity in this space, Intel's Ponte Vecchio. For more details on this design, see my post HOT CHIPS: Two Big Beasts. The key quote from that post:

There are over 47 tiles (chiplets) manufactured on five different process nodes. It is over 100B transistors.

Now that's heterogeneous integration!

The term "heterogeneous integration" still has a problem, namely, what do we call one of these designs? My vote is to use "system-in-package," which also abbreviates nicely to "SiP." So heterogeneous integration is the technology to create a SiP.

Obviously, the contrast to heterogeneous integration is homogeneous integration. That's basically what we call a system-on-chip or SoC. The biggest drawback to homogeneous integration is in the name—everything has to be in the same semiconductor process. That is a challenge if you need to integrate very different blocks such as photonics, RF, analog, DRAM, MRAM, and more. The challenge is economic, not technical. We know how to put DRAM on a logic die, for example, but in effect, you are paying for DRAM even on all the parts of the chip that are not DRAM (so the DRAM masks are blank there). Another issue with homogeneous integration is that the die can get very big. If it gets too big, it can exceed the reticle limit, and so not be manufacturable. But even if it is below the limit, big die do not yield well compared to the same area of silicon in, say, four separate smaller die.

COTS Chiplets

There are plenty of technical challenges to a more automated heterogeneous integration flow. But I think that the most interesting questions are in the commercial area. And let me emphasize that I don't have the answers (and neither does anyone else) to these questions yet.

COTS stands for "commercial off the shelf." Normally, it is used in specialized industries such as defense to distinguish chips that can simply be purchased, as opposed to specialized chips that have to be designed for that purpose. To my mind, one of the most interesting questions about heterogeneous integration is whether COTS chiplets will be available. In perhaps the most extreme case, will I be able to build a SiP with a microprocessor from Intel, a GPU from NVIDIA, and a 5G modem from Qualcomm?

There are already a few COTS chiplets (or chiplet stacks) that are available, such as high-bandwidth memory (HBM) and CMOS image sensor (CIS) vision/AI subsystems.

For this market to expand, and for off-the-shelf chiplets to be available, there are several big questions:

• Will chiplets be available as silicon or just as IP for license?
• Who will hold the inventory if there are actual chiplets available?
• Will it be an "if we build it, they will come" type of market, or a chiplet-on-demand kind of market where chiplets are only manufactured after a firm order is received?
• Who will manage the manufacturing operations of chiplets?
• Will new companies come into existence to create/serve this market?

These questions largely come down to who will take the financial risk: the end-user, a middleman such as a distributor, the company that designed the chiplet, the foundry, or someone else. As with any value chain, all the participants will want to maximize the revenue/profit that they receive and attempt to commoditize the other suppliers. Of course, if everyone is too aggressive about this, then it risks killing the goose that lays the golden eggs. Or, in this case, killing the goose that hasn't laid any eggs yet and so ensuring that the market never comes into existence.

Learn More

See the Cadence corporate blog post Heterogeneous Integration (HI) vs System on Chip (SoC) – What’s the Difference?

 

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