HOT CHIPS Day 1: Hot Chiplets

I've said before that HOT CHIPS is one of the best places to absorb the zeitgeist of what is going on in the most advanced chip designs. After all, at HOT CHIPS, the presentations are about many of the most advanced designs in any given year. For example, a couple of years ago it became obvious that chiplets or systems-in-package were going mainstream, at least for high-performance designs. I wrote about that in my post HOT CHIPS: Chipletifying Designs.

Today's post takes a 2022 look at what is going on in the technologies for putting more than one die in a package. I'm just going to use the name "chiplets" for this (Intel calls them "tiles") since all the terminology hasn't completely settled down yet. So here's the chiplet view of HOT CHIPS 2022's program.

Several of the presenters quoted Gordon Moore from his original paper in Electronics, the one that proposed what came to be known as Moore's Law. Later, on page 3, he said:

It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.

If there was a theme to this years HOT CHIPS, I think that would have to be it.

NVIDIA’s Hopper GPU: Scaling Performance

The first presentation of the conference was by NVIDIA talking about their Hopper GPU (as in Grace Hopper, see my post Grace Hopper Celebration of Women in Computing if you don't know who she was). This is also known as the H100. The presentation was by Jack Choquette & Ronny Krashinsky.

The chip has 80B transistors and so is one of the largest monolithic chips...so no chiplet angle, right? Not so fast, it has the world's first HBM3 interface and so is designed to be packaged with HBM3 memory stacks. It is designed to have 5 stacks and a memory bandwidth of 3 TB/s (although the photos seem to show 6 sites).

AMD Instinct MI200 Series Accelerator and Node Architectures

This was presented by Alan Smith and Norman James. The first level of chiplets in this design is that it consists of two die joined together with a 500 GB/s in-package infinity fabric.

But wait, there's more. That double-die goes into a package with I/O chiplets and eight stacks of HBM2E.

Intel’s Ponte Vecchio GPU: Architecture, System and Software

This chip got a walkon part in Pat Gelsinger's keynote when he held up a chip a couple of times. I wrote about Ponte Vecchio last year, see my post HOT CHIPS: Two Big Beasts.There are over 47 chiplets  manufactured on five different process nodes. It is over 100B transistors. This year's presentation by Hong Jiang was more about the software and scale-out aspects.

Biren BR100 GPGPU: Accelerating Datacenter Scale AI Computing

The presentation was by Mike Hong and Lingjie Xu. This design is bigger than the reticle limit. It also yields better by using smaller die. It has 77B transistors.

Passage—A Wafer-Scale, Programmable Photonic Communication Substrate

Nicholas Harris of Lightmatter presented their Passage product. He started with an introduction to silicon photonics and the kinds of devices. If you don't already know this, see my post Silicon Photonics. As you can see from the above diagram, Passage is a sort of photonics interposer that allows ASIC die to be integrated into larger systems. It solves the "beachfront" problem that there is not enough edge on the die for all the fibers you might want to connect by going vertically. It provides what Nicholas called wafer-scale photonics interconnect.

Heterogenous Integration Enables FPGA-Based Hardware Acceleration for RF Applications

This presentation actually described some work done under the DARPA chips program. In this case, integrating die from Texas Instruments (TI), with FPGA die from Intel, using Intel's EMIB packaging technology.

Enabling scalable application-specific optical engines (ASOE) by monolithic integration of photonics and electronics

Christoph Schulien of Ranovus presented their monolithic platform ODIN. The focus was actually on not using chiplets, but integrating the electronics and photonics onto the same platform.

Scaling of Memory Performance and Capacity with CXL Memory Expander

There's not really a chiplet angle on this presentation by Samsung's Sung Joo Park. But it does tie in nicely to my post about the Sunday tutorial on CXL HOT CHIPS: CXL Tutorial.

Academia

The first day finished up with presentations from academia, although one was actually from Arm. They were:

• HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces by Abhishek Bhattacharjee & Rajit Manohar, Yale University
• Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs by Alfio Di Mauro, ETH Zurich
• Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration by Kathleen Feng, Stanford
• Arm Morello Evaluation Platform - Validating CHERI-based Security in a High-performance System by Richard Grisenthwaite, Arm

The last Arm presentation on Morello I have written about before, in my post What Is a Capability? CAP, CHERI, and Morello. I will cover the presentation at this year's HOT CHIPS in its own post.

Day Two

Day two coming later this week. For full details of the HOT CHIPS this year, see the program page.

 

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