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At IEDM in December, the Sunday preceding the conference proper consists of two short courses, traditionally one logic-related and one memory-related. I always attend the logic one, since that is the most relevant to EDA and the broad semiconductor industry. The number of memory design starts is limited, even though the volume for each one is enormous. This was really brought home to me years ago when VLSI Technology hired a new corporate counsel, Larry Grant, from Micron. He was amazed in executive staff meetings at how many designs we were involved with as both an ASIC foundry and company with its own products (in PC chipsets, and GSM/CDMA chipsets primarily). As he put it, "at Micron we put a couple of designs into production each year, whereas here we put a couple into production most days". Cadence's business is driven largely by the number of design starts, and that means SoCs, analog, and so on. Of course, the memory companies are customers too, but that is ~6 customers out of the whole market, doing perhaps a dozen designs a year (a lot more than in Larry's day, even if his "couple of designs a year" was already an exaggeratedly low number).
Of course, there is embedded memory on pretty much all SoCs, but even that was covered (by Eric Wang of TSMC) in the logic course. I'll write about what he said another day. Today, I will cover the opening presentation of the short course titled EUV Lithography: the Road to HVM and Beyond by Anthony Yen of ASML. You probably already know this, but in case not, ASML is the company based in Netherlands that is the only company in the world to produce EUV steppers. When the three companies with leading-edge manufacturing say they are inserting EUV into production at some their second-generation 7nm (Intel calls it 10nm) node, it is ASML steppers they are inserting. When GLOBALFOUNDRIES decided to stop chasing the bleeding edge and focus on more profitable business, they were giving up on EUV too (and have a couple of steppers to sell you, if you are interested, probably for a lot less than the list price of over $100M... each).
I'm going to assume some working knowledge of EUV already. And, on the basis that you can only learn something if you almost know it already, you should read some of my previous posts if you do not. The most relevant ones are:
That last post is quite old, but it lays out what all the problems were a couple of years ago, many of which have only been partially solved, and the current status of which is covered in this post. For example, if you don't know why EUV requires a vacuum and reflective optics, or what a pellicle is, then read that last post.
EUV has a wavelength of around 14nm. Current ArFl lasers have a wavelength of 193um and so require double patterning for pitches of less than 80nm. The attraction of EUV is that at 7nm a lot of the tight masks in the FEOL, MOL, and the lowest layers of BEOL can be single patterned. This saves by both reducing the number of reticles required, and reducing the number of mask steps. This is not just a cost reduction, it is a reduction in turnaround time to get from a wafer start to finished goods.
EUV started back in 1986, over 30 years ago, when synchrotrons were used for the radiation. It was independently proposed by Lawrence Livermore National Laboratory (yes, there was lithography in the next valley over from Silicon Valley) in 1988, and work was done at Bell Labs in the same era. A company EUV LLC was incorporated in 1996 to continue the development. It tied the industry together, with a management board of semiconductor companies, and work being done by national laboratories and equipment manufacturers such as ASML, but also others in that era. By 2002 that work culminated in the Engineering Test Stand.
ASML took over commercialization. They shipped their first full-field tool in 2006, and made strides since then (see the above table).
One of the biggest problems was the power source. Originally, this was developed by a separate company, Cymer, but ASML acquired them in 2012. If the power could not be got high enough then EUV would never be able to process enough wafers per hour to be faster and more cost-effective than multiple-patterning. When you first hear about how the optics work, vaporizing 50-80,000 droplets of molten tin per second with high powered lasers, it sounds like something out of a James Bond movie (or more like an Austin Powers movie—although no sharks are guiding the lasers). Only about 5% of the laser energy is turned into EUV, and since the reflective optics absorbs about 30% at each mirror, very little of that reaches the wafer. In 2017, the 250W power level was demonstrated, which is generally regarded as the threshold for HVM.
The EUV source looks more like a Formula-1 racecar engine than a light source. The light is gathered by a big mirror called the collector, with one focus where the droplets are zapped by the laser, and another, known as the intermediate focus, where the light leaves the generator and enters the stepper itself. One big issue has been keeping the collector clean since it is in a dirty environment (tin droplets are being vaporized by lasers nearby). From the intermediate focus, the light is directed by mirrors to the mask (which is itself a mirror) and eventually onto the die on the wafer.
The word "mirror" makes you think of something like your bathroom mirror, or even a telescope mirror (which is silvered on the front surface). But those would simply absorb EUV. The mirrors (and the mask) are complex constructions of multi-layers of silicon and molybdenum, relying on Bragg reflection to (mostly) reflect. A big issue is that it is very hard to make a mask that doesn't have defects that print. A defect that is too small to see can develop into something larger after all those layers are built up. In any case, the size of the mask and the size of a defect are very different. I've heard it described as using a satellite to look for a golf-ball in the state of California. A lot of progress has been made towards making masks with tiny numbers of defects.
Another issue is keeping the mask clean. In refractive optics (normal non-EUV optics) the mask is covered with a pellicle, a thin film that ensures that any contaminant is not in the plane of the mask and so will not print. There are two problems with EUV pellicles. First, almost everything absorbs EUV so that there are limited choices of material. Second, with reflective optics, the light path goes through the pellicle twice. Keeping the mask clean needs two approaches: one, keep the scanner from having any contaminants in the first place, and second to use a pellicle.
Anthony didn't talk about it, but I've heard that initial EUV insertion is with pellicles. First, they are not ready. But the initial use is for contacts and cut masks where most of the mask is dark and not printing, and a particle will not show up at the photoresist on the wafer.
One big issue in EUV lithography is variability, or stochastics as it is usually called today. Everything is tiny, and so the number of photons, molecules in the chemically amplified resist, are small enough that there can be a lot of variability. If there are a million photons to make a contact, then if the dose is a few hundred short it doesn't matter. If there are only a few hundred photons, and a billion contacts, there is a good chance that some of them have way too few. Then you can get a "closed hole" meaning a missing contact (or a missing cut leaving two lengths of interconnect still joined). If you read the first two posts that I linked to at the start of this post, you'll see that a lot of the focus is on the stochastics. That's just for 7nm. It is harder still to deal with at 5nm and beyond. Without going into a lot of technical detail (because I'm not a photoresist expert) I'll just say that lots of progress seem to be being made.
Work is also going on on new absorbers (to make masks) and new resists, such as nanoparticle resists, which rely on a completely different physical process from the chemically amplified resists (CAR) being used up until now.
The next challenge is to build a high numerical aperture (NA) machine. Don't worry if you don't know what numerical aperture is, just think of it as a measure of the goodness of the optical system. These systems require a lot of vertical height to fit the optics and are two stories high. Note the person on the left of the above diagram for scale.
EUV will go into HVM in 2019 to extend semiconductor scaling. ASML shipped 10 NXE3400B systems in 2017, 12 in the first 3 quarters of 2018, with 6 more planned before the end of 2018.
Beyond 7nm, there are continual improvements on tools, masks, and resists needed to take 0.33NA EUV into the next decade. There is a roadmap in place but a lot to be done. The first 0.55NA EUV system is targeted to ship by the end of 2021.
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