IEDM, the International Electron Devices Meeting, took place last week. It was also the RISC-V Summit that week, so I missed most of Tuesday at IEDM since I went down to San Jose. My overview of the RISC-V Summit is in a post earlier in the week What's Happening in RISC-V Land?

The format was the same as usual, with:

• Tutorials on Saturday
• Two parallel short courses on Sunday, one on logic, one on memory
• Plenary session on Monday morning
• Press luncheon on Monday
• Then a dozen sessions running in parallel, ranging from accessible invited papers to extremely deep technical dives

There was also a panel session on Tuesday evening, a career lunch on Tuesday, an exhibit hall, various privately organized evening events, and probably more stuff I was not even aware of.

I will write several blog posts early in the New Year (Breakfast Bytes goes on hiatus at the end of this week until January 2). I attended the logic course on Sunday, which I will cover. One of the presentations in the short course and a couple of the sessions I attended were both about automating Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO). I'll cover them in a post. It is one of the areas most pertinent to EDA.

And in a smart move by the conference organizers to keep everyone there, the very last time slot of the conference included 5nm CMOS Production Technology Platform Featuring Full-Fledged EUV, and High Mobility Channel FinFETs with Densest 0.021um² SRAM Cells for Mobile SoC and High-Performance Computing Applications from at huge team at TSMC led by Geoffrey Yeap. I'll cover what they said in its own post. (Especially since I missed the Cadence Marketing department's holiday party to attend it!)

In this post, I'll summarize a few other presentations that I don't think justify writing about on their own. By the way, we are not allowed to photograph anything at IEDM, even in the keynotes. However, every paper has a paper in the proceedings, usually with diagrams (surprisingly, even the plenary session keynotes). So I'll use illustrations from there when appropriate.

Background to EUV

First, a bit of shorthand. LE stands for litho-etch. A normal single exposure. LELE or LE-2 is double patterned, LE-3 is triple patterned, LE-4 is quadruple patterned. In this post, we are only talking about 193i (light at 193nm wavelength with immersion lithography), and although the terminology is not really correct, we won't distinguish between LELE and SADP (self-aligned double patterning). EUV is extreme-ultraviolet, a 13.5nm light source with reflective optics running in a vacuum produced by just one company, ASML.

NA stands for numerical aperture, and is a measure of how much light gets captured and used by the optical system in the stepper. Bigger numbers are better.

ASML's CEO, Martin van den Brink, gave the second plenary keynote. It was titled Continued Scaling in Semiconductor Manufacturing Enabled by Advances in Lithography. That's very generic, but really it was about recent history and the future of EUV lithography. Since ASML is the only company that supplies EUV steppers, the industry roadmap and the company roadmap are one and the same. Inevitably, any post about EUV sometimes sounds a little like a commercial for ASML. By the way, if you didn't know, ASML is based in the Netherlands. The mirror supplier is Carl Zeiss in Germany.

The picture is the current generation, but with nothing in the picture for scale, it is hard to appreciate how huge it is. I saw one for real at imec a couple of years ago. However, I wasn't allowed to take any pictures of it...especially as it had the covers off so it looked more like the picture here.

In the four years since I returned to Cadence, I have written about EUV quite a bit. At first, I was skeptical that it would even work. The issue everyone talked about back then was the source power, and whether it could be got up to 250W, which was regarded as the minimum for EUV to have a high enough wafer throughput to be acceptable in high-volume manufacturing.

But there were other issues. One was whether there was any material from which it would be possible to make a pellicle. In refractive optics (193nm light and earlier), there are lots of materials that are transparent. The pellicle is a thin film that covers the reticle and ensures that any particle of contamination is kept out of the focal plane of the optics and so will not print. EUV has two issues with pellicles, that EUV is absorbed by almost everything, so there are very few available materials, but also that with reflective optics, the light path goes through the pellicle twice. So if the pellicle is 90% transmissive to the 13.5nm light, then only 81% (90% x 2) gets through.

All the mirrors in the optical path (I think that there are 12 in the current machines) only reflect about 70% of the light (a "normal" mirror such as you might use in a telescope absorbs EUV light). That is one reason for all the emphasis on source power and photoresist sensitivity: amazingly, less than one percent of the light from the source makes it to the wafer.

Current Status of EUV

But I was wrong to doubt, at least in the sense that EUV is in high-volume production at the three leading-edge manufacturers. The graph Martin showed says that by the end of Q2 there were 38 installed systems. It is nearly six months later so I assume it is a little higher now. The current product, the NXE-3400C, is rated at 170 wafers per hour. So that is the status of the first generation of EUV lithography.

This graph shows both the importance of a pellicle (the left-hand column has zero printing defects) and the progress ASML have made in reducing what they call "fall on defects" over time, getting it down close to zero even with no pellicle.

The Future: High-NA

Martin said that progress is required in several areas to enable single patterning to continue further. Their goal is to maintain EUV single patterning all the way down to a minimum pitch below 20nm (note that this is nothing to do with the headline number of the process—there is nothing 7nm on a 7nm process). This result would enable dimensional scaling to continue through the next decade at least.

The areas for improvement are:

• Improved EUV photoresist materials with better resolution and simpler chemistry, to reduce photon shot noise and chemical fluctuations (at these dimensions, the placement of individual molecules of chemical amplification material starts to be important)
• Improved material for the EUV absorber on the mask (which is a mirror). TaBN is the current standard absorber, but for low-k₁ imaging, the three-dimensional effect of the mask results in degradation of image contrast and edge placement errors
• Improved source power (they have demonstrated 500W in the lab, about twice the current number)
• Moving the numerical aperture (NA) from the current 0.33 to 0.55

The graph below shows the economics for various levels of multi-patterning (remember LE-4 means LELELELE), the costs of the current EUV system (with single patterning and multi-patterning), and the expected costs of the next-generation high-NA system (with just single patterning required down to 20nm pitch at least).

One issue that will rear its head is cost. In his keynote at Arm TechCon, Greg Yeric of Arm research predicted the billion-dollar EUV stepper. Or, as Martin put it rather more indirectly:

Manufacturing equipment may evolve to a level of complexity that is unable to sustain a healthy ecosystem

These things are huge, by the way. If you've ever seen an EUV stepper, they dwarf the people standing beside them (plus there is all the power system for the laser in the subfloor underneath). High-NA machines are huger (ok, I know that's not really a word), two stories high to accommodate the light path. Martin had a picture of one, but it is not in his presentation in the proceedings (and remember we were not allowed to take photographs). So here's one from another ASML presentation:

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