IEDM: The World After Copper

I remember Gary Patton, the CTO of GLOBALFOUNDRIES, telling me once that research seemed to have flipped, and whereas he used to have most people working on transistors and interconnect was an afterthought, now it was the other way around. Just scaling the existing copper interconnect to get to the next generation was no longer enough.

At IEDM in December, there was a special session called Interconnects to Enable Continued Scaling. There were invited presentations by:

• Arm and Georgia Tech
• IBM
• imec
• UT Austin and GLOBALFOUNDRIES
• Stanford
• Applied Materials

I won't try and go through every presentation separately. Instead, I'll mostly focus on the ones from imec and from Applied Materials, which both look at candidates for future interconnect to replace copper. First, a look at why the future of copper is, to use the word of the year, problematic.

Copper Interconnect

This is going to be a highly simplified description, partially because I'm not a process technologist, and partly because, like most aspects of semiconductor manufacture, there are a lot more detailed steps involved in reality.

In the dim and distant past, interconnect was mostly aluminum-based. A layer of aluminum (or perhaps different metal like a sandwich of Titanium and Tungsten, written TiW) was put across the whole wafer, and then the unwanted metal was etched away to leave the wires.

Exactly twenty-one years ago, IBM and Motorola surprised everyone at IEDM 1997 by announcing two copper interconnect processes. The drivers for its introduction were higher performance and that it was much more reliable than aluminum, that only had a couple more process generations of life in any case. More more details on the history, see the section towards the end Twenty Years of Copper in my post IEDM 2017.

There's a lot of interconnect on a chip. On a typical IBM server chip, there are 17 levels of copper wiring, adding up to 30-50 miles of interconnect. When copper was first introduced in 1997, it was the 0.22um node (220nm). Today, the wires are 1/30th the width they were back then.

The manufacturing process is very different and is known as a Damascene process (or dual Damascene to emphasize that the via and the metal above are manufactured together). This is named after the pottery technique where metals are inlaid in ceramics. The copper interconnect is done in an analogous way, the dielectric is patterned where the interconnect wires are required, then the whole wafer gets a layer of copper, and then chemical-mechanical-polishing (CMP) is used to grind away the unwanted copper leaving just the copper that is in the dielectric below the surface, filling both the wire and the vias underneath.

In fact, copper can't be put directly against the dielectric, since it diffuses into it. So a liner is required, which is typically a tantalum (Ta) compound. Each via has a liner down the sides. An additional complication is that the liner goes across the bottom of the via too, meaning that the current flowing in the interconnect has to pass through that little bit of barrier metal, so the barrier resistance can be important. Each longer interconnect wire also has a liner. See the image to the right, where the green is copper, and the liner is blue.

The big challenge in scaling interconnect is that the resistance is getting harder to deal with, and is a major impact on performance. One reason is simply that thinner wires have a higher resistance than fatter wires. But a more severe problem is the barriers. The thickness of these doesn't really scale, or at least not at anything like the same rate as the overall process scale factor. This means that each via and each wire increasingly consists not of copper, but of the barrier metal that is there to make the interconnect manufacturable. So the copper actually gets thinner even faster than the interconnect is scaling.

Another issue is the grain size of the copper, which feeds into both resistance and reliability. At these dimensions, copper resistivity is increasing. This also leads to some counterintuitive facts, such as cobalt being lower resistance than copper for short runs, but copper for longer runs.

Georgia Tech: The Physical Design Perspective

A good metric when looking at processes at chip scale is the wire resistance per gate pitch. This is increasing almost exponentially, whereas capacitance is increasingly more linearly. The result is that wire resistance is going up (per gate pitch) but capacitance (per gate pitch) is going down. FinFETs have made device capacitance more important. It used to be that gates had to be 1000 logic gates apart to see the same wire resistance as the transistor. But now it is just tens. However, capacitance use to be 10 logic gates and now it is 30 or 40 (because the FinFET capacitance is high).

Result: more and more interconnect is resistance-limited, not capacitance-limited.

This leads to the question: why not increase the wire width and reduce the spacing? We will have more capacitance (closer plates) but resistance will be down, so it might be a good tradeoff. But to find out, you actually need to look at a circuit, create libraries, and go through the physical design process. The result: some gain in performance. Power dissipation drops since fewer buffers are needed. Next challenge: interconnect process variability with multiple patterning. Capacitance is not very sensitive to geometry variation, but resistance is extremely sensitive, resulting in 12% delay variability. However, making the wires thicker lowers the variability (because it lowers the resistance).

But these tricks can only get you a little way. Eventually, we will need to go beyond copper.

Imec: Metals Beyond Copper

As already discussed, there is a dramatic increase in line and via resistance for copper beyond 20nm. Thinner TaNRu liner gives some margin over TaNCo (because TaNRu allows a thinner barrier). But even with a metal cap, imec's predictions are that with a CDline below 10nm will not meet Jmax of 1MA/cm2. So, end of the road for copper. What next?

The table above shows all the individual metals (not alloys). The X-axis is the melting temperature, and the Y-axis is basically the resistance. The shaded light green area is where to look: metals that have a melting point at least as high as copper (for reliability) but a lower resistance for the same geometry.

Not all of these materials are fab-compatible. The viable alternatives are iridium (Ir), rhodium (Rh), ruthenium (Ru), and cobalt (Co). There is a lot of data on Co and Ru since there is a lot of work being done on them. One challenge with copper was that it needs a barrier or it will have poor electromigration performance as the copper migrates out of the wire (it is very mobile). Do these alternatives need barriers?

• Co needs a barrier (similar to Cu)
• If clean, Ru can be barrierless. Atomic Layer Deposition (ALD) and physical vapor deposition PVD) are clean. But chemical vapor deposition (CVD) needs more attention to make it clean.

Another challenge is the different coefficient of thermal expansion leading to cracks in BEOL during packaging. These alternative metals might be worse than copper... but imec did finite element modeling and found no dramatic difference with 20% higher stress for Co, and 10% for barrierless Ru. So not a showstopper but slightly higher.

Looking at EM reliability is not straightforward since barrierless Ru means that classical dual damascene Cu test vehicles not applicable. The numbers are not there yet when doing complete failure analysis involving self-heating and high current densities. Another area to explore is Ru plus air gap, which looks promising from very early measurements.

Other metals are promising, but two challenges are the seam or buried voids (during manufacture) so that the metal doesn't occupy all the space it is meant to, and high recrystallization temperature, that can have collateral damage on other parts of the chip. Not all of these metals (if barrierless) adhere well to the dielectric,

Conclusion: Ruthenium has much better EM performance, but its lower thermal conductivity (than copper) leads to higher heating slopes. Ruthenium + air-gap also looks reliable at first glance but needs more research.

AMAT: Interconnect Trends

Applied Materials, as an equipment manufacturer, sees a broad selection of the work going on across the industry. As Mehul Nalk said:

The industry is focused on how to manage contact resistance, and interconnect resistance.

On contacts, he said, tungsten contacts are reaching their scaling limits, and tungsten chemistry prevents reduction of the ALD TiN thickness, meaning that the volume of tungsten keeps going down node over node. There is a tungsten seam in the middle of the contact too, meaning that W contacts are reaching their scaling limit. Cobalt provides an escape since we can reduce the ALD TiN thickness and they use a seam-free cobalt fill with CVD and Co reflow. Cobalt is the better material (compared to W) going forward, with a 3-4X improvement in line resistivity (see graph to right).

In fact, exactly a year before at IEDM 2017, Intel had talked about using Co at 10nm (60% reduction in contact resistance). M0 and M1 they changed to Co, too, with a 40% lower via resistance.

The reason not to switch everything to Co is that line resistance crosses over with copper, as I said earlier. Co is better than Cu when the area is less than about 450mm2, 12-15nm CD. Large-scale Cu replacement requires metal CDs to drop below 12-15nm. For M0 and M1 the lengths are short, so via resistance is the most important. For M2 and above, interconnect is longer, and the resistance of the interconnect itself is the dominant factor.

Mehul said that there is a lot of interest in maximizing the volume of copper and extending it as a material, but:

there's only so much you can do with the thickness of the barrier before it all falls apart.

Beyond copper and cobalt, there are possibilities with ruthenium, iridium, and molybdenum. Mo is better than Cu at CDs between 1-15nm. Iridium is better than Cu at CDs between 15-20nm. So iridium looks the best but there are lots of details that would need working out about damascene fill and whether we can polish with CMP. These all need to be answered before you can pick a metal for post Cu and Co.

• Barriers: Co needs a barrier, but Ru and Mo don't. Ir does. So no clear winner at this point.
• Maturity: Co fill is more mature than Ru. One issue is that Ru doesn't reflow.
• Resistance: there is no crossover seen with Ru versus Cu likely due to voids. Co to Cu crossover at 12-15nm CD (see graph to right).
• Reliability: Cu, Co, Ru with Co Cap. Ru both have no failures. Co or Cu not so good.

Overall scorecard for Cu replacement: Co is most mature. Ru has fill and CMP issues that need to be worked out before it can be chosen.

The situation today: Cobalt is the first new conductor to be introduced in 20 years replacing W at contact. Cu extendability continues with ALD barrier.

Summary

It is looking increasingly likely that ruthenium is in your future.

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