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At IEDM in December, one of the papers in the very last session (a sneaky trick to get us all to stay) was TSMC announcing their 5nm process. The paper actually had the cumbersome title 5nm CMOS Production Technology Platform Featuring Full-Fledged EUV, and High Mobility Channel FinFETs with Densest 0.021um2 SRAM Cells for Mobile SoC and High-Performance Computing Applications and was authored by Geoffrey Yeap, S.S. Lin, Y.M. Chen, H.L. Shang, P.W. Wang, H.C. Lin, Y.C. Peng, J.Y. Sheu, M. Wang, X. Chen, B.R. Yang, C.P. Lin, F.C. Yang, Y.K. Leung, D.W. Lin, C.P. Chen, K.F. Yu, D.H. Chen, C.Y. Chang, H.K. Chen, P. Hung, C.S. Hou, Y.K. Cheng, J. Chang, L. Yuan, C.K. Lin, C.C. Chen, Y.C. Yeo, M.H. Tsai, H.T. Lin, C.O. Chui, K.B. Huang, W. Chang, H.J. Lin, K.W. Chen, R. Chen, S.H. Sun, Q. Fu, H.T. Yang, H.T. Chiang, C.C. Yeh, T.L. Lee, C.H. Wang, S.L. Shue, C.W. Wu, R. Lu, W.R. Lin, J. Wu, F. Lai, Y.H. Wu, B.Z. Tien, Y.C. Huang, L.C. Lu, Jun He, Y. Ku, J. Lin, M. Cao, T.S. Chang, and S.M. Jang.
One disappointing thing about the paper was the lack of detail. Typically, these process papers have at least a few pitches, even if not in the paper but on the screen (which we are banned from photographing). In fact, in the press lunch, Scotten Jones of IC Insights complained about this and the conference organizers admitted that they almost refused it. In fact, they said they refused another paper on a 3nm process (they didn't say from whom) due to the lack of detail. Talking of which, during the short courses on Sunday, TSMC's Jin Cai presented on Device Technology for 3nm and Beyond. This was more of an overview of the challenges and options, rather than a description of TSMC's plans. I will cover that in a separate post, along with the presentation by Chris Wilson of imec on Novel Interconnect Techniques Beyond 3nm Technologies. These two presentations together did a good job of laying out the options for continuing Moore's Law for another process generation or two.
Geoffrey Yeap presented. Here are the key parameters of the process. Some of this I have covered before when TSMC presented on 5nm in both the 2019 Technology Symposium and the 2019 OIP Ecosystem Symposium. I wrote about what they said then in TSMC Technology Roadmap and TSMC OIP: Process Status.
One major impact of EUV on the process is that for the first time ever, the total number of masks has reduced from the previous (7nm) process. The graph is normalized (to one at 16nm) so you can't actually read off the number of masks. Based on the numbers presented in the paper, that there are over 10 layers of EUV, each replacing at least four masks, which means the white area on the graph must be at least 30 masks and the overall mask count looks to be around 75 (the blue area looks about 2.5X the white) and would have been over 100 without EUV. Scotten Jones, who has a business modeling the costs of processes, reckons that there are ~70 masks in TSMC's 5nm, so not far off eyeballing this bar chart. Anyway, you can do your own tea-leaf reading from the graphs and the data below.
Here are some of the important attributes of 5nm disclosed in the paper and the presentation at IEDM. Anything in "quotes" is directly from the paper in the proceedings.
Having mentioned Scotten Jones above, let me provide a link to his post at my old employer SemiWiki IEDM 2019 – TSMC 5nm Process. He is much more knowledgeable than me on process stuff, and has some speculation there on things like the process pitches, EUV doses, and more.
Bottom line: TSMC has developed a 5nm process that will be in high-volume manufacturing very soon (first half of 2020) with a planned "fastest ramp ever". The previous fastest ramp was roughly going from a standing start to 50,000 wafers-per-month over three months. Given TSMC's market share of the foundry business, this is presumably the most significant process for the next couple of years. If you buy a new phone late this year, it will almost certainly contain some chips built in it.
Next...3nm. Watch for my reports on the TSMC Technology Symposium in April.
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