At IEDM in December, one of the papers in the very last session (a sneaky trick to get us all to stay) was TSMC announcing their 5nm process. The paper actually had the cumbersome title 5nm CMOS Production Technology Platform Featuring Full-Fledged EUV, and High Mobility Channel FinFETs with Densest 0.021um2 SRAM Cells for Mobile SoC and High-Performance Computing Applications and was authored by Geoffrey Yeap, S.S. Lin, Y.M. Chen, H.L. Shang, P.W. Wang, H.C. Lin, Y.C. Peng, J.Y. Sheu, M. Wang, X. Chen, B.R. Yang, C.P. Lin, F.C. Yang, Y.K. Leung, D.W. Lin, C.P. Chen, K.F. Yu, D.H. Chen, C.Y. Chang, H.K. Chen, P. Hung, C.S. Hou, Y.K. Cheng, J. Chang, L. Yuan, C.K. Lin, C.C. Chen, Y.C. Yeo, M.H. Tsai, H.T. Lin, C.O. Chui, K.B. Huang, W. Chang, H.J. Lin, K.W. Chen, R. Chen, S.H. Sun, Q. Fu, H.T. Yang, H.T. Chiang, C.C. Yeh, T.L. Lee, C.H. Wang, S.L. Shue, C.W. Wu, R. Lu, W.R. Lin, J. Wu, F. Lai, Y.H. Wu, B.Z. Tien, Y.C. Huang, L.C. Lu, Jun He, Y. Ku, J. Lin, M. Cao, T.S. Chang, and S.M. Jang.

One disappointing thing about the paper was the lack of detail. Typically, these process papers have at least a few pitches, even if not in the paper but on the screen (which we are banned from photographing). In fact, in the press lunch, Scotten Jones of IC Insights complained about this and the conference organizers admitted that they almost refused it. In fact, they said they refused another paper on a 3nm process (they didn't say from whom) due to the lack of detail. Talking of which, during the short courses on Sunday, TSMC's Jin Cai presented on Device Technology for 3nm and Beyond. This was more of an overview of the challenges and options, rather than a description of TSMC's plans. I will cover that in a separate post, along with the presentation by Chris Wilson of imec on Novel Interconnect Techniques Beyond 3nm Technologies. These two presentations together did a good job of laying out the options for continuing Moore's Law for another process generation or two.

TSMC's 5nm

Geoffrey Yeap presented. Here are the key parameters of the process. Some of this I have covered before when TSMC presented on 5nm in both the 2019 Technology Symposium and the 2019 OIP Ecosystem Symposium. I wrote about what they said then in TSMC Technology Roadmap and TSMC OIP: Process Status.

One major impact of EUV on the process is that for the first time ever, the total number of masks has reduced from the previous (7nm) process. The graph is normalized (to one at 16nm) so you can't actually read off the number of masks. Based on the numbers presented in the paper, that there are over 10 layers of EUV, each replacing at least four masks, which means the white area on the graph must be at least 30 masks and the overall mask count looks to be around 75 (the blue area looks about 2.5X the white) and would have been over 100 without EUV. Scotten Jones, who has a business modeling the costs of processes, reckons that there are ~70 masks in TSMC's 5nm, so not far off eyeballing this bar chart. Anyway, you can do your own tea-leaf reading from the graphs and the data below.

Here are some of the important attributes of 5nm disclosed in the paper and the presentation at IEDM. Anything in "quotes" is directly from the paper in the proceedings.

• This is a "full-fledged EUV" process with over 10 EUV single patterning layers, each replacing some number of layers of multipatterned, which improves both yield and cycle time. The paper says >4 layers, the diagram in the paper shows 5, and Geoffrey said >3. I suspect that just means that some layers would require triple patterning without EUV, some would require quadruple patterning, and I'm not sure where 5 comes from, perhaps something involving self-alignment.
• High-mobility channel FETs. In the Q&A, Geoffrey was asked if that was both the P and the N channel, and said it was just one. But he wouldn't say which (I'm assuming P-channel since they usually need more help, and I'm assuming Ge is added, but it could be some other III/V material). "if you know, you know", was his last word on the topic.
• 0.021um² SRAM cell, approximately 1.35X density improvement, "consistently achieved very high yield in 256Mb SRAM and logic test chip: >90% peak yield and ~80% average yield (without repair) in 256Mb HC and HD SRAM". 
• Around 1.84X logic density improvement vs 7nm. 15% performance improvement or 30% power reduction (not both, obviously). Overall chip size reduction is expected to be 35-40% given reasonable ratios of logic, memory, and analog.
• "Innovative approach of offering up to seven Vt’s for each transistor type enables product design to meet the needs of power efficiency in mobile SoC, and peak speed requirements in HPC. The 5nm platform technology also offers a set of critical HPC features such as extremely low Vt (eLVT) for 25% peak speed over 7nm, and HPC 3-fin standard cells for additional 10% performance gain."
• "innovative implementation of gate-contact-over-active and unique diffusion termination for extra logic density, and EUV-based gate-patterning process."
• "Tightest pitch Mx RC and Vx Rc kept relatively similar to previous 7nm node as shown in Figure 8 by using EUV patterning, innovative scaled barrier/liner, ESL/ELK dielectrics, and Cu reflow."
• "Additional HPC features such as super-high-density (SHD) MiM, which has 4X higher capacitance density than typical HD-MiM, produces ~4.2% faster Fmax by minimizing transient drooping voltage, and achieves ~20mV Vmin reduction in a CPU test chip."
• "High-speed SerDes was successfully developed by optimizing FinFET driving strength, and capacitance/resistance by using special-purpose high-speed devices. Figure 16 shows that the PAM4 transmitter demonstrating highest speed of 130Gb/s with 0.96pJ/bit and nominal 112Gb/s with 0.78pJ/bit energy efficiency."
• As already reported at OIP, the process has passed qual and is on the fastest ramp planned of any TSMC process ever. Risk production started in March 2019. HVM in the first half of this (2020) year.

Summary

Having mentioned Scotten Jones above, let me provide a link to his post at my old employer SemiWiki IEDM 2019 – TSMC 5nm Process. He is much more knowledgeable than me on process stuff, and has some speculation there on things like the process pitches, EUV doses, and more.

Bottom line: TSMC has developed a 5nm process that will be in high-volume manufacturing very soon (first half of 2020) with a planned "fastest ramp ever". The previous fastest ramp was roughly going from a standing start to 50,000 wafers-per-month over three months. Given TSMC's market share of the foundry business, this is presumably the most significant process for the next couple of years. If you buy a new phone late this year, it will almost certainly contain some chips built in it.

Next...3nm. Watch for my reports on the TSMC Technology Symposium in April.

 

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