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At IEDM in December, Jin Cai of TSMC presented Device Technology for 3nm Node and Beyond during the short course on Sunday. He divided his presentation up into four parts:
Until about 2000, we were in the era of "happy scaling" where we could use thinner gate oxides, lower voltage, and channel doping to get regular process nodes that were faster than earlier nodes, with higher density, and the same (or lower) power. This was known as Dennard scaling. For the decade after that, we used Hi-K metal gate (HKMG) and strained silicon until we got to 20nm. After that, we switched from planar transistors to FinFETs. Since then, we have needed to use DTCO to add boosters to the process, which also allowed further optimizing of standard cells, such as reducing track counts, using fewer transistors in the FinFETs, self-aligned contact, single diffusion break, contact over active gate, with more in the future.
TSMC is now on the fourth generation of their FinFET technology. Logic density up 6X, power at fixed speed about 0.25X, speed at fixed power up by 1.65X. A couple of days later, TSMC presented details of the 5nm process (although we all got the proceedings when we registered so we could read the details earlier). I covered that in my post Details of TSMC's IEDM Presentation on N5 a few weeks ago.
The options going for transistors are in the diagram above. Of course, bulk is limited to about 28nm (at 20nm the leakage was already too high, even though TSMC did have a short-lived 20nm planar process). FinFET looks like it can go to 3nm. Next, there are gate-all-around (GAA) processes such as nanosheets and nanowires, and more speculatively, since it is a completely different manufacturing process, carbon nanotubes (CNT) and 2D-TMD (transition metal dichalcogenide).
The ideal thing is to squeeze as much as we can out of FinFET technology by optimizing the fin width and shape to minimize the problems to minimize resistance and capacitance. Fin width reduction improves short channel effect, and there is a sweet spot for maximum drive current. Various process changes can reduce the gate dielectric equivalent oxide thickness (EOT) to get better short channel control.
Reducing contact resistance can be attacked both by tweaking resistivity and also by increasing the contact area. Reducing resistivity can be done by increasing doping near the contact and adding more germanium for the PFET. Using a "wrap-around" contact can maximize the S/D contact area as in the diagram.
Further optimization can be done with DTCO, such as optimizing the gate-cut process to enable shorter gate extension over the active region, which reduces the standard cell length.
The advantages of nanosheet are improved short channel effect (from the GAA architecture) and flexible width design (unlike FinFET). The challenges Jin called out are N/P balance, bottom sheet effectiveness, inner spacer, and gate length control. multi-Vt engineering. Nanosheet also has improved layout efficiency, especially with large W (wide sheets and more than 2 of them) as in the diagram.
A big challenge is the inner spacer, needed to reduce the S/D parasitic capacitance, and the complexity of the process architecture to create it.
Another challenge is the bottom sheet. Stacking many sheets is expected to lose performance since the bottom sheet carries less current but adds the same capacitance.
Nanowire transistors give the best gate control since the gate length is scalable well below 10nm. But there is a limited effective channel width per footprint.
High mobility channels are required to enable Vdd scaling (such as germanium or CNT). Also, naturally thin materials such as 2D TMD (MoS2, WSe2, etc.) or 1D CNT help with gate length reduction. There is progress in this area but with lots of outstanding challenges to meet all the required parameters.
Germanium has mobility advantages since it has high electron and hole mobility. In the presentation that TSMC gave about their 5nm process, they said that they used high mobility material in one of the transistors, and the consensus of a few people around me was that they were using Ge in the PMOS channel.
The ultimate gate length scalability are CNT transistors. The best p-contact resistance is 6.5KΩ at 10nm. The big challenge with CNT is that some of them are conductive and so they need to be purified using ultracentrifugation to 99.997% pure. They then have to be aligned on the wafer in some way, such as self-assembly or multiple CNT transfer. But there is progress being made. In 2013, Stanford published a paper on a 1-bit microprocessor built with 178pMOS CNFETs, and last year MIT created a 16-bit RISC-V microprocessor with 14,702CMOS CNFETs (both papers published in Nature).
The above table compares the options. FinFET is in production. In the short term, the solutions that are in development are nanosheets and nanowires, and using Ge to improve gate mobility. Further out, still in the research as to whether they are even feasible, are the 2D materials and carbon nanotubes (CNT).
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