What Comes after 2nm GAA?

There are three companies that currently pursue the smallest geometries, what I've heard called "the race to the end of Moore's Law". One is based in Korea, one in Taiwan, and one in the US. So the obvious place to go to find out what is in the funnel of ideas for the future is...Belgium. Leuven, which is just outside Brussels, is where imec is based, and where a lot of pre-competitive research is done. For more background on imec, see my post If It's Tuesday This Must Be Belgium. My First Visit to imec. There are about 4,500 people doing research at imec, some working for imec but many seconded from semiconductor companies. Not everyone at imec works on semiconductor research, it is also involved in health and life sciences, smart cities, and more.

As it happens, the most advanced processes also share another feature, they use EUV (13.5nm wavelength light). The equipment for EUV lithography comes from just one supplier, ASML, based in Veldhoven (a suburb of Eindhoven). It is about sixty miles from Leuven, but Belgium is not a large country and Veldhoven is in the country next door, the Netherlands.

At the recent 2021 Symposia on VLSI Technology and Circuits (VLSI 2021), imec announced some results for a type of transistor called a "forksheet". Then, at the 2021 International Interconnect Technology Conference (IITC 2021), imec announced some work done on advanced interconnect metallization schemes using intermetallics and air gaps. Since a new process node generally requires changes to both the transistor and the interconnect, these two approaches have the potential to form the basis for a generation after 2-3nm.

In the longer term, there is an expectation that a boost in density will come from complementary FETs (CFETs), where the N and P transistors are stacked vertically. However, for the time being, nobody really knows how to build this structure economically. For some background on CFETs, see my post ITF: CFETs and New Interconnect.

Forksheets

For a few years now, the increase in density from process node to process node has not depended just on scaling of the features of the process, but also on design-technology co-optimization (or DTCO). For more on that, see my post How Low Can You Go? but basically DTCO involves adding specific features to the process so that the height of standard cells (measured in tracks) can be reduced, and often so that the size of the SRAM cell can be reduced too. Forksheet transistors are no different. One of the limiting factors to cutting another track out of the standard cell height is the space required to keep the N and P transistors apart. A standard cell consists of a number of P-transistors across the top, and a number of N-transistors across the bottom, but design rules with GAA transistors (and FinFETs, and planar, for that matter) limit how close these two groups can get, which in turn limits whether another track can be cut out.

On the left in the diagram is the 2nm gate-all-around (GAA) nanosheet transistor design. On the right is the forksheet, with a wall between the N and P transistors, which allows both the N and P transistors to be closer and also allows the channel nanosheets to be wider and thus higher drive. Also worth pointing out explicitly is that the forksheet is not GAA since there is no gate on the inner sides up against the wall. The key number is that the gap between the p-transistors and the n-transistors can be reduced to 17nm, which is about 35% of the state-of-the-art for FinFETs. This has the potential to reduce cell height from 5 tracks to 4.3 tracks.

Here's a quote from Naoto Horiguchi, who I talked to for more details for this post. He is director of CMOS device technology at imec:

From 2022 onwards, it is expected that today’s leading-edge FinFET transistors will gradually give way to vertically stacked nanosheet transistors in high-volume manufacturing, as the FinFET fails to provide enough performance at scaled dimensions. Process limitations will however pose a limit to how close the nanosheet’s n and p devices can be brought together, challenging further cell height reduction. The new forksheet device architecture, which is a natural evolution of the GAA nanosheet device, promises to push this limit, allowing track height scaling from 5T to 4.3T while still offering a performance gain. Alternatively, with a forksheet design, the available space can be used to increase the sheet width and as such further enhance the drive current. Our electrical characterization results confirm that the forksheet is the most promising device architecture to extend the logic and SRAM scaling roadmaps beyond 2nm leveraging the nanosheet integration in a non-disruptive way.

The TEM images above show both the forksheet transistor (with the wall) and a GAA nanosheet transistor. On the right is along the forksheet channel.

Interconnect Metallization

I didn't even know there was an International Interconnect Technology Conference but, at this year's recent conference, imec announced developments in interconnect technology. There are two big challenges in interconnect: resistance and liners. As the metal lines and the vias get narrower, they naturally have higher resistance. To some extent, for lines, this can be compensated by making the metal thicker vertically since that makes the cross-section larger. Liners are a problem for two reasons. One is that they are largely a constant thickness, so as the lines and vias get thinner, less of the cross-section is low-resistance interconnect and more is higher-resistance liner. Also, at the bottom of any via, the current flowing up or down the via has to go through the liner at the bottom of the etch.

For a good primer, read my post IEDM: Novel Interconnect Techniques Beyond 3nm. One of the facts presented was that for pure metals, the only possible choices are platinum group metals like rubidium, cobalt, nickel, molybdenum, niobium, and chromium. All other metals are worse than copper in that they are higher resistance, or they are incompatible with copper since they melt at a lower temperature (and so it would be impossible to use them, and then use copper for the thick upper layers of interconnect). 

In that post, I said (see the above diagram):

There are also more complex compounds, not just single elements, that show excellent figures of merit, and will be needed to address resistance increases.

It was development in this area that imec announced at the interconnect conference. It announced research performed on stochiometric AlCu and Al₂Cu films, giving a resistivity as low as 9.5μΩcm. Other aluminides were also studied, including AlNi, Al₃Sc, AlCu, and Al₂Cu.

imec has also been studying how to manufacture with these materials, using an advanced semi-damascene integration using direct etch of patternable metal to achieve a higher aspect ratio, and using air-gaps to replace low-K dielectric to reduce capacitance. Unfortunately, air-gaps have poor thermal conductivity which creates challenges with Joule heating, which imec has also been modeling.

As imec summarised in its press release:

These results experimentally support their promise to be used as new conductors in advanced semi-damascene interconnect integration schemes, where they can be combined with airgaps for improved performance. In this combination, however, Joule heating effects are becoming increasingly important. This was predicted by combined experimental and modeling work in a 12-layer back-end-of-line (BEOL) structure—implementing new metals and airgaps. 

Transistors and Interconnect

These two developments have the potential to form the basis of a next-generation process coming after the 2nm processes already in development at semiconductor manufacturers. Potentially, other materials could be used for very local interconnect in the middle-of-line in the same way that Cobalt is sometimes used today.

imec in the Press

Normally, imec is too specialized to get noticed outside of our industry. But just as semiconductors in general have moved into the mainstream due to shortages and politics, so has imec. Just a few days ago, Bloomberg published a piece about them: The U.S.-China Tech Conflict Front Line Goes Through Belgium. I think Bloomberg gives you some free articles, so you should be able to read it even if you don't have a subscription.

Sign up for Sunday Brunch, the weekly Breakfast Bytes email.