Intel eASIC: Linley and DARPA

At the recent Linley Processor Conference 2021I, Intel's Massimo Verita talked about Intel's eASIC N5X. He was asked during the questions whether this used Intel's EMIB packaging technology that provides buried connections inside the package to allow a primary die to be linked up to a variety of I/O die, depending on the interfaces required. I actually wrote about this in one of my photonics posts, How to Design Photonics If You Don't Have a PhD: iPronics and Ayar Labs, since Ayar Labs is working with Intel and using EMIB to connect its photonics interfaces. Massimo said that eASIC is actually built in TSMC's 16nm process and so does not use Intel packaging.

DARPA and Intel

However, he pointed out, Intel has just announced an agreement with DARPA to bring the eASIC technology onshore and it will then have access to EMIB. José Roberto Alvarez, who is the senior director, CTO Office of Intel Programmable Solutions Group (what used to be Altera) said:

We are combining our most advanced Intel eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it’s all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process.

The announcement was a three-year partnership based on eASIC with the usual DARPA-style catchy but somewhat forced acronym: SAHARA (Structured Array Hardware for Automatically Realized Applications):

Intel will use its structured ASIC technology to develop platforms that significantly accelerate development time and reduce engineering cost compared to traditional ASICs. Intel will manufacture these chips using its 10nm process technology with the advanced interface bus die-to-die interconnect and embedded multi-die interconnect bridge packaging technology to integrate multiple heterogenous die in a single package.

Structured ASIC

A bit of history. Intel acquired Altera in 2015. Altera had been the number two FPGA company for years (behind number one Xilinx). Then, in 2018, Intel acquired eASIC. eASIC provided what was called "structured ASIC" and was supposed to hit a sweet spot between FPGAs and full ASIC designs. FPGAs were seen as easy to design but expensive unit cost, too power-hungry, too slow, but didn't involve programming any masks. A full ASIC design was seen as optimal unit cost, optimal power, optimal performance...but too expensive and time-consuming to design. Structured ASIC was meant to be the sweet spot in the middle. Various approaches were tried, some involving just a few masks and some involving all masks but creating a turnkey automatic transition from an FPGA. In practice, this was usually a sweet spot without enough business in it and proved more like a valley of death. Many companies, from LSI Logic, to Altera and Xilinx themselves, had programs in this space and they all went nowhere. It seems that Intel, with its eASIC family, is trying again. eASIC, at least before Intel acquired them, got costs down by reducing programming to a single via layer. From the pictures in Massimo's presentation, it looks like that is now two via layers.

Things might be different this time. Doing a full SoC design is now so expensive that there is an even bigger gap between the design costs and time to market compared to an FPGA, and so now there is a bigger gap for structured ASIC to insert itself. Perhaps more significantly, the volume required to justify an SoC design is now so large that few markets are large enough. In mobile, it is obvious handsets clear that bar, it is less clear whether basestations do. DARPA and DoD have always had the problem that their design volumes are low but often FPGAs don't satisfy their needs, and the design costs for an SoC are just too high if you only need a few chips (one per jet fighter, say).

Massimo's Linley Presentation

Massimo started with a similar comparison to that I made above, between FPGAs, structured ASIC, and ASIC (so SoC). He said that Intel is focusing on the markets that are attractive for the technology: 5G, AI, cloud and storage, edge compute, and mil-aero. I think what makes these attractive, apart from timeliness, is that they have enough volume that FPGAs are not that attractive, but not so much volume as to justify either designing a full ASIC or attracting standard product semiconductor companies to supply into the market.

He had some numbers comparing structured ASIC to the other two technologies: 50% lower power (and zero power for any unused logic) compared to FPGA; smaller die and so smaller unit price; half the development time compared to an ASIC, with an automatic FPGA replacement flow.

As I said above, the diagram Massimo shows implies that it is programmed with two via layers, one to replace the LUTs of an FPGA, and one to program the interconnection between the units of the fabric.

The architecture looks like in the diagram above. The grid in the middle is the array of gates and memory devices (10K Bram blocks and 128 bit register files). Down in the bottom left is the Hard Processor System, which is actually a quad-core Arm A-53 with memory interfaces. One of the interesting questions when Intel acquired Altera was whether they would continue to use Arm for the processor on each FPGA or switch to something more akin to Intel's Atom (x86) processor. Intel stuck with Arm and on his last slide Massimo describes this processor as "IntelFPGA compatible".

The design flow is pretty much what you would guess or expect. I don't think it is compulsory, but I think it is expected that designs will be prototyped in FPGAs and then there is a flow to take the proven design and move it into the eASIC physical design and signoff process.

Project SAHARA

You can see Intel's announcement of SAHARA on its website.

I summarized Linton Salmon (then a DARPA program manager) on the topic of the DoD's problems with the design and manufacture of semiconductors in my post Open-Source IP in Government Electronics. Linton, who had worked in TI's mobile group earlier, summed it up in a single sentence showing the DoD's unique problem:

In DoD, I've yet to see a total production that is more than the samples that we would send out in the commercial world.

The effect of that is that production costs are almost irrelevant, but design costs are hugely important. Obviously from that point of view, Intel's eASIC product line is attractive for several reasons:

• Lower power and smaller physical form-factor than Intel's FPGAs
• Lower design cost and faster time to market than a full ASIC
• US manufacturing in Intel's 10nm fabs (in Oregon, New Mexico, and Arizona)

This is not going to have an immediate effect, but under Pat Gelsinger, Intel re-entering the foundry business and building new fabs in Arizona (with fabs in Europe hinted at) to provide capacity for the business could turn out to be one of the most significant events of early 2021. It will take years to unfold but, as newspapers used to say back when newspapers were a thing, watch this space.

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