How to Design Photonics If You Don't Have a PhD: iPronics and Ayar Labs

Last week was the virtual event CadenceCONNECT: Photonics Contribution to High-Performance Computing. The opening keynote was by Odile Liboiron-Ladouceur who leads a team working on photonics at McGill University in Montréal. You can read about that keynote in my post Photonic Integration — From Switching to Computing.

But how do you design silicon photonics if you don't have a PhD on the topic? I'm sure she'd love you to hire one of her grad students, which might be one solution, but the two presentations that followed the keynote were by iPronics and Ayar Labs on approaches where you don't need to do design at the polygon and waveguide level, they take care of the low-level details. iPronics has an approach analogous to gate-arrays in which the design requirements are specified at a high level and the detailed "place and route" is taken care of by its technology. Ayar Labs are working on chiplets that you use advanced packaging technology to integrate with your electronics.

iPronics

Daniel Pérez López, the CEO of iPronics, presented Programming General-Purpose Photonic Processors. He pointed out that programmable photonic circuits are evolving from special purpose to general purpose, with the structures programmed after they have been fabricated. Since this is analogous to an FPGA (field-programmable gate array), iPronics calls these FPPGA (field-programmable photonics gate arrays). The topologies do not have to be hexagonal, like above, but lots of other possibilities exist. Such as triangular meshes:

You can program these FPPGAs manually with a tedious flow that requires a lot of specialized knowledge. iPronics allows a much more automated flow analogous to how you program a normal FPGA: mapping the requirements onto the topology and then using automated place and route.

The iPronics Smartlight user-interface looks like this:

Everything you need is in the box!

Ayar Labs

Ayar Labs have actually made a previous appearance in Breakfast Bytes in my post about More than Moore titled HOT CHIPS: Chipletifying Designs.

Last week's presentation was by Mark Wade, Ayar Labs' CTO,  and was titled The Transition to Chip-to-Chip Optical I/O. Ayar has been working with Intel on designs using Intel's proprietary EMIB (embedded multichip interconnect bridge), which allows interposer-free multi-die designs without going all the way to its true 3D technology called Foveros. The motivation for their work is that the amount of power dissipated in electrical I/Os continues to rise, it is unclear if anything will come after 112G SerDes (my own prediction is that ideas used in wireless modems such as QAMx will be used rather than just relying on amplitude and open eye-diagrams).

Ayar have collaborated with Intel to show that they can build their TeraPhy into an Intel gate-array (the old Altera) using Intel's EMIB technology, just like other potential I/O chiplets. The EMIB technology doesn't use interposers but allows multiple die to cheaply be integrated into a package. Here's a slide from an Intel presentation I attended that shows a bit more detail about how it works under the hood. Obviously, this diagram doesn't include a photonics chiplet, but they are linked up in the same way, with the obvious difference that the optical interconnect needs to be brought out on the top of the package for connection to fiber.

Another piece of the puzzle is the laser. That is not on TeraPhy. The laser is an external unit called SuperNova, which is a multi-wavelength source. Having a completely external laser simplifies the packaging. Also, CPUs, GPUs, and FPGAs are often running at 85°C or even as high as 110°C, and lasers need to keep below 55°C, so this is also a much simpler thermal solution.

Note that since there are no signal integrity issues with photonics, the laser can be relatively far from the TeraPhy equipped chip, and the signals being driven can be at data center scale (up to 2km).

Since the laser is external, Ayar is working with an ecosystem to standardize the interface. The consortium is called CW-WDM MSA (Cadence is an observer member).

Mark thinks that we are on the cusp of a dramatic change in how we add optical interconnectivity straight from the package at the level of shelf, rack, row, and whole systems. These can be "logically connected but physically distributed systems" that you can do with photonics but cannot really do electrically.

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