Linley: Western Digital's RISC-V Strategy

Western Digital acquired SanDisk in 2016. In 2017, Martin Fink, then the CTO of Western Digital, announced that it would convert all the cores used on its devices to RISC-V. This was one of the first solid commitments to RISC-V in a commercial setting.  

As I said in my post at the time, RISC-V Workshop, Milpitas:

He then made his big announcement, that Western Digital would be migrating all their cores to RISC-V. But they will do more, and they will do it in the open-source spirit. They will develop open-source IP building blocks for the community, actively partner, and invest. He gave an example of Dave Ditzel's company Esperanto, where Western Digital has just made an investment in high-end core development (this set up Dave, since he was the next presentation after the keynote, but you'll have to wait for tomorrow's Breakfast Bytes to read about it).

Back then, Martin said that Western Digital shipped 1B cores per year, and it would soon rise to 2B cores per year.

In 2019, he was back to talk about SweRV EH1 which is a 32-bit 9-stage dual-issue core. You can read all the details in my post RISC-V Cores: SweRV and ET-Maxion. The core is open-sourced and you can download all the views from Github.

Then, in 2020, Martin retired, and his successor Siva Sivaram came and talked about the family of SweRV cores. As I said in my post The 2020 RISC-V Summit:

WD actually has three cores in the SweRV family, all of which are open-sourced. First is the original SweRV EH1 core, which has already been adopted by several other companies. The new core is the EH2, which is lower power and also dual-threaded, which is a big help in WD's main market involving a lot of I/O. The third core is smaller, the EL2, intended for sequencing. It has a 4-stage pipeline but is also higher performance than other microcontrollers WD might have picked.

Linley Processor Conference

At the recent Linley Spring Processor Conference, it was the turn of Zvonimir Bandic to present its latest core, in a presentation titled A Linux-Compatible 64-bit High-Performance In-Order RISC-V CPU Core. He started with an overview of the whole SweRV core roadmap, shown in the diagram above. The core Zvonimir was discussing is the EHX3, the bottom arrow on the diagram. Two other changes on the diagram that you might miss. The first generation of cores were all open-sourced, and there are dozens of adopters. Now Codasip has taken over supporting customers using them. The other change is that more recent cores, the ELX2(S) security core and the EHX3 are no longer open-source. They will obviously be used within Western Digital but will also be shared with their partners.

Western Digital thinks of itself as a data company. I'm sure that you know it makes disk drives and flash memory, but it is also moving towards providing data services too. So it needs a Linux/Android processor that is also low power. Data services envisioned include:

• Capacity and performance management
• PCIe device virtualization
• Data protection and availability
• Security

He showed the above simplified diagram of how a typical flash controller might be implemented using multiple SweRV cores. A quadcore version of the EHX3 is used as the main CPU, and multiple EHX2 (or EHX2(s)) are used for the NAND channels, security, and power management.

The internal block diagram of the EHX3 is shown above. It is a 3rd generation core implementing the RV64GBC ISA using an 8-stage pipeline. It is implemented at 7nm, with a target frequency of 1.8 GHz with coherency support for up to 8 cores using Tilelink, as in the diagram below:

There is SMP support for 2, 4, or 8 cores, with a shared L3 cache of 0, 1, 2, or 4 MB, and using the Tilelink coherency protocol. This is a RISC-V standard intended to help drive interoperability. It is high bandwidth and low latency. There is a normal AXI system bus.

The die plot above shows the same four-core shared L3 cache implementation.

And here is an 8-core implementation of the EHX3.

In simulation-based benchmarks, the EHX3 is achieving 1.1 to 1.16X of its performance targets on things like Specint.

Zvonimir wrapped up listing the expected deliverables for the EXH3:

• RTL IP
• Hardened blocks
• Verification test benches
• Processor support packages
• Performance-optimized toolchain

The processor is currently in beta.

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