Machine Learning in EDA

Yesterday, in my post Cerebrus: The Future of Intelligent Chip Design, I talked about our latest product to use machine learning (ML) techniques to great effect. Although they are all slightly different, machine learning is also known as artificial intelligence, deep learning, and neural networks. I'll put all those terms in, although I'm just going to use machine learning in this post (plus, Mr Google will like this post better).

Even though they may seem to run for a long time (a week is not unusual in some cases), EDA tools have historically been parsimonious with using computer resources, and wasteful of using designers' time. If an elephant never forgets, an EDA tool is the opposite—it never remembers anything from one run to the next. If a synthesis tool like Genus, say, needs a timing constraint changed (to add a false path, say) then the designer has to add a line to the SDF file but the synthesis tool starts over at parsing the SystemVerilog, redoing all the elaboration, and so on. This is wasteful in two ways. Firstly, if the tool could be made smarter, so that it automatically recognized the omitted false path, then it could have restarted optimization with all the data structures still in memory. And secondly, the designer had to analyze the results of the first run, make the change, launch the tool again, and then do it all over again a few minutes, hours, or days later. One wastes computer time, and one wastes designer brainpower.

Machine learning means tools to get better results faster. Like any advantage, this can be taken in various ways:

• Just take the better results, because they are...well...better
• Take the time saved and use it to get even better results (for example, doing more verification)
• Use the improved performance to reduce cost by requiring fewer engineers to achieve the same result
• Use the improved performance to allow lower-skilled engineers to work at the level of the most skilled engineers
• Use the improved flow to create a better methodology for the next (or other) similar chips
• All of the above

Yesterday

Apart from the name, not a lot about the Cerebrus announcement yesterday would have been a surprise. We have discussed early results in keynotes for the last couple of years. For example, here's a slide from Anirudh's keynote at CadenceLIVE Americas just last month.

But Cerebrus is not the first Cadence tool to be improved by machine learning, just the latest one.

JasperGold

The first product to get deep learning capability added was JasperGold, our formal verification solution. In 2019, I was in Israel for CadenceLIVE Israel (still called CDNLive back then) and I spent some time with Ziyad Hanna to discuss what we were calling "Smart Formal Technologies". You can read about that in my post Machine Learning in JasperGold. Sometimes I think up clever titles, but this one just tells you what you're going to get. You can read Ziyad's update last year in my post Jasper User Group: The State of Formal in 2020 (that covers a lot of cloud capabilities as well as deep learning).

If you want to know a lot more about JasperGold's machine learning capabilities, then the post I mentioned above has all the details. Here's just one paragraph to give the flavor of one key capability:

On-the-fly exploration and on-the-fly exploitation. This is the JasperGold Expert System with the user in the loop. We can train, then use the ProofGrid where the tool gets a list of properties, knows the engines, and starts to learn the patterns of properties and engines. Then the machine learning predictors (weights) are used to make JasperGold more adaptive. Ziyad said it's a bit like having a strategy for Vegas: you have two machines, you need to decide which machines to try and for how long, how much you want to invest, when to switch, how to invest your $100 and maximize your return. With formal, you may have a budget of 50 cores and two hours and you want to maximize the number of properties proved. There is also on-the-fly learning where you can train on a subset of say 100 or 1000 properties, and then extrapolate to the rest of the properties.

Xcelium ML

The next product with machine learning is Xcelium ML, which is our simulation tool for functional verification. I wrote about that when we announced it last year in my post Xcelium ML: Black-Belt Verification Engineer in a Tool. There are more details about how the technology is implemented in my second post Under the Hood of Xcelium ML. Machine learning is used to improve the seed and vector choices in constrained random simulation, resulting in fewer runs, less simulation, but with the same coverage.

Allegro X

During Anirudh's keynote at CadenceLIVE Americas that I pulled a slide from earlier in this post, he announced our machine learning capability in the PCB world, with Allegro X. I covered it in my post that day Allegro X, the Design Platform for the Next Generation of Intelligent System Design. As I pointed out in that post, PCB design is about a lot more than just the PCB:

it involves not just the board but cables and connectors, signal integrity, thermal analysis, RF, multiple design groups, and a whole portfolio of design tools.

Well, you still need to worry about connectors and cables, but that portfolio of design tools can now be run from a single cockpit, Allegro X. In addition to pulling a lot of technology together and making some of it cloud-enabled, it also incorporates machine learning for placement and routing of devices on the PCB.

Cerebrus

Then, yesterday, Cerebrus (or Cerebrus Intelligent Chip Explorer to give its full name). This post is long enough already, so I'll just point you to yesterday's post Cerebrus: The Future of Intelligent Chip Design and give you one image:

The Future

One of the most useful phrases I learned for dealing with editors and financial analysts who were trying to get me to reveal something I should not is "we have no announcements to make at this time". So I'm not going to pre-announce anything here. But don't be surprised if more products get machine learning capability.

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