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At CadenceLIVE Europe back in November, one of the presentations was by Mohamed Naeim titled Design Enablement of 2D/3D Thermal Analysis and 3-Die Stack. Mohamed is officially a Cadence employee, but he's also a Cadence PhD resident at imec and works on projects that hopefully end up shipping in real Cadence products. As a PhD student, he is also associated with Université Libre de Bruxelles (Free University of Brussels). I had coffee with him and his predecessor as Cadence PhD resident, Giuliano Sisto when I visited imec last June. You can read about that in my post My Second Visit to imec.
The motivation for his work is that there are some power and performance improvements using 3D-IC because of wirelength shortening. In this post, 3D-IC means putting one die (or later two) on top of each other, not interposer-based designs. However, stacking two die on top of each other results in temperature increases due to heat confinement between the two dies. 3D thermal analysis is built on top of the thermal analysis of each die, so good 2D thermal analysis is a pre-requisite.
The diagram above shows the experimental setup. Voltus is used to produce a power map used for thermal simulation. Then Celsius is used to produce a thermal power map. That enables thermal-aware analysis of power, IR drop, and EM. The experimental design used was a many-core cluster with 256 32-bit RISC-V cores, no L2 cache, and a MemPool group. It is 2M standard cells with 384 memory macros. Naively splitting the design in two somewhat randomly to produce a 3D-IC provided performance improvement due to the shorter wirelength, but as expected, there was a temperature increase compared to the 2D baseline (building the whole chip as a single die).
There are three potential ways to improve the situation:
The diagram above shows the baseline (all on one die) on the left and the 3D version with the whole design split 50-50 into a top and a bottom die.
Here's how the various layers stack up in the 3D version. For the bottom die, the substrate thickness is 300nm with a total thickness of 6.2um. The bottom die has a backside power delivery network (BSPDN). For the top die, there is no backside metal, the Si substrate thickness is 500um, the same BEOL thickness of 1.4um, and a total thickness of 501.4um. A normal frontside power delivery network.
But there's more than just the two die. There is everything from a PCB at the base, with solder balls, and also a heat spreader and a heat sink on the top, not to mention a bonding layer in the middle.
Power density evaluation with an operating frequency of 1.5GHz and static power analysis with an activity of 10%. The power density of the logic die increased due to a smaller footprint and inserted buffers. The logic die is 2.15X higher power density than the 2D base case.
Mohamed compared the 2D-Mix, MoL, and LoM. The bottom die substrate is 300nm due to BSPDN. 3D-IC increases max temperature by 29.9°C for MoL and 27.2°C for LoM (see the graph above).
Mohamed moved on to stacking three die instead of just two. The motivation for this is that SoCs are memory dominated. For example, a many-core SoC with an L1 cache, 64 cores, 4 DMA channels, and 128-bit wide L2 cache has 68% of the silicon area occupied by memory. By using a 3-die stack, more memory macros can be pushed to the upper dies providing more PPA improvement.
I won't step through the whole flow in detail, but the above diagram shows how Cadence tools (mostly Integrity 3D-IC) were used to generate the 3-die stack.
This stack is memory-on-memory-on-logic with only memories on the upper two die, as shown above. This is still a work in progress, so Mohamed did not yet have power and thermal results to report. I guess he'll be back at CadenceLIVE Europe again next year.
The next steps are to implement 3-die stack for a large SoC and to do a full thermal analysis.
Bottom line for these multi-die stacks is that PPAC has to become PPACT (power, performance, area, cost, temperature).
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