Breakfast Bytes Blogs

At the recent TSMC OIP forum, Yufeng Luo presented Optimized Digital Design, Implementation, and Signoff on TSMC N3. He should know all the details. After all, he's the VP of R&D for the Innovus Implementation System, which is at the heart of our "Digital Full Flow". N3 is, of course, TSMC's next-generation process node after N5 (and its N4 optical shrink). For more details on TSMC's process roadmap, see my post TSMC Technology Symposium: All the Processes, All the Fabs. It is still a FinFET process, with risk production planned for 2021 and volume production in 2022.

Yufeng started off by discussing design trends but I'm going to leave that out. There are literally dozens of blog posts on Breakfast Bytes discussing things like 5G and deep learning silicon, and unless you've been such a recluse that you've not attended a keynote in about the last two years, you already know all this.

But then Yufeng dug down a bit deeper into migration requirements to get to N3:

• New transistors
• New design rules
• New multi-patterning requirements (yes, even with EUV)
• Process variability
• More corners and power modes
• Threshold voltage levels
• Wire resistance scaling issues
• Timing closure with target PPA
• IC packaging complexity (more than Moore)
• And even...more (hehe)

Device and Library Cells

N3 has smaller FinFETs and, obviously, higher density. The devices switch faster. The power is lower.

On the cell front, N3 has variations on cells for different performance and area points, and there are cell density requirements.

As a result, early cell type selection analysis is needed during synthesis, efficient early architecture selection is needed based on generic gate delay and area calculations, and extremely tight integration is needed between synthesis and placement for area optimization.

Wire Scalability

We are hitting the limits of wire scalability. The picture above looks like one of those YouTube videos of 10,000 colored dominos being knocked over, but actually it is a real signal route. Buffers need to be inserted. The higher metal layers are lower resistance so the signals need to get up there if they are going far.

But that causes problems. Wiring density doesn't scale with transistor density. Metal layers are getting taller and more resistive, which has a broad impact on everything to do with timing. And getting up to those higher layers causes all sorts of congestion on the lower layers that the signals have to pass through to get to the higher layers.

Interconnect and Via Resistance Variability

EUV isn't a panacea for lithography. There are multiple effects that impact resistance sensitivity such as line edge roughness (LER), shot-noise, random distribution of atoms in the photoresist. These can cause both interconnect and via variation.

So in the diagram above, the two seemingly identical vias can have very different resistance and need to be extracted and modeled statistically for accurate delay calculation.

Digital Flow Progression

How does Cadence's digital flow address this?

There is a saying that the best time to plant a tree is twenty years ago. Well, the best time to start collaboration on an advanced process like this is...well, obviously not 20 years...eighteen months ago. We have a structured technology development partnership for a year and a half, with an early patterning/EUV study tapeout to find out more about how development was handling the process.

There are N3-specific features that get developed in partnership. After all, there's little point in putting something in the process if the EDA tools cannot handle it. And no need to handle an issue in the tools if it can be addressed more easily tweaking process.

• Floorplanning and placement rules for standard cells, boundary cells, macros
• Congestion avoidance in routing
• Low-voltage LVF (Liberty Variation Format) accuracy and signoff DRC checks

At the end of that, there was an N3 SoC tapeout with early PDK.

The results obtained from that testchip put the flow well on the way to TSMC certification.

Certification

I'm not going to go into all the details of the enhancements to the tools, the algorithms, and the flows. Ultimately, the most important thing is whether the flow (and the chips!) work. Since we announced certification on N3 the day before Yufeng presented, it's clear that everything works. You can see more details in the table above. The tools are all certified and there is a jointly developed reference flow for optimizing silicon, validated on testchip silicon.

Summary

Cadence is in production deployment in 17 of the top 20, making it the leader in advanced node.

N7, N6

• Used on more than 150 7nm tapeouts
• Industry-leading PPA
• Elegant full-flow solution

N5, N3

• Certified at N5 with PPA leadership
• N5 testchips completed and active deployments in-progress
• Certified on N3
• N3 testchips completed

Easy deployment and collaboration model (Cadence, TSMC, and mutual customers) with a quick ramp in all areas.

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