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EDA tools have a primary challenge: to be good at whatever it is they do. They have a second challenge, which is to get support from the rest of the ecosystem, such as synthesis libraries (yeah, I used to be at Ambit Design Systems). But signoff tools have an especially severe problem. Nobody will use them unless the foundries that will manufacture the chips accept the results.
Recently, we announced that the Pegasus Physical Verification System is certified by TSMC at 16nm and below. Specifically, for all variants of N16, N12, N7. That means that companies can tape out designs in these processes, use Pegasus to perform physical verification, and then TSMC can fabricate them without design-related manufacturing defects. These are full signoff physical verification flows including design rule check (DRC), layout versus schematic (LVS), DFM fill, DFM enhancer, and others.
The obvious question is "what about N5 and N3?" but we already announced Pegasus certification on these nodes! You probably missed it, I certainly did, but in our N3 announcement last month, Pegasus was included in the certified flow, and in our announcement about N5 last year, Pegasus was included there, too.
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The way I phrased that might make it sound like only now can a customer tape out a design. But in fact, we have dozens of customers and over 100 tapeouts already on TSMC nodes. Some customers have done multiple tapeouts. And these were full signoff tapeouts, in the sense that no other physical verification system was used in parallel. Pegasus has been in a sort of intermediate state since it was first announced in July almost exactly two years ago. We did a controlled rollout. Now it will go into the price book for unrestricted release.
If you notice, the "largest" node that is covered in the announcement is N16. We are working with TSMC on the more mature nodes, which actually are much easier to cope with but still require certification. The plan is to support all nodes up to 180nm by the end of the year.
You can run Pegasus as a standalone to verify blocks, chips, or packaging. But Pegasus is also integrated into the Innovus, Virtuoso, and Allegro environments so that it can be run as part of the flow, rather than as a separate job.
Having named our physical verification system after a flying horse, it had better be ready to head for the clouds, right? In fact, Pegasus is ready for both hyperscale on-premises data centers, and Cadence cloud. It can scale to hundreds of CPUs. What's more, it plays nice, not requiring any machine with ridiculous memory limits or lots of cores. In fact, this allows you to run on older machines instead of competing with all the other groups for the newest machines. What's more, even if eventually it gets a huge number of cores, it doesn't wait for them before it gets going. Even if some of the machines die, it doesn't stop the whole run. For example, one tapeout run went up to over 900 CPUs (crowd: we want a thousand!) but you can get 12-hour runtimes for 7nm big chips at 400-500 CPUs where other systems require thousands. The turnaround time is very predictable.
The scalability is nearly linear. Physical verification is actually a good candidate for massive scaling since different processes don't need to interact like they do in, say, simulation and placement. About the only thing that is inherently easier to scale is library characterization with hundreds or thousands of cells and dozens or hundreds of corners. We've done characterization runs using over 50,000 cores.
One challenge with doing physical verification with big chips in modern processes is that early runs can produce literally millions of DRC/LVS violations. Smart Verify is a part of Pegasus for this early stage, allowing you to run a big chip in about two hours with low numbers of CPUs, and focus on the systematic violations that can produce so many violations as to overwhelm the design team. All Pegasus customers use this—the time is not in doing the runs but in debug.
At the recent CadenceLIVE Americas, the very last presentation slot of the whole conference had Steve Chin, director of IC engineering at FPGA company Efinix saying that they used Pegasus to tape out all their FPGA family to a number of different foundries and all the chips worked without requiring any respins. As Steve said, "coming back with a chip that does not work in a small company like us kills the project and can kill the company." Pegasus flew in successfully.
Pegasus now has certified decks from N3 up to N16 at TSMC. It is a massively scalable production tool. It has a robust infrastructure that is cloud-friendly, providing low cost of ownership. It runs on heterogeneous machines and doesn't require all machines to be available to start. In particular, there is no need to wait for in-demand high-end machines, it can run on machines that many other applications cannot.
Learn more about Pegasus on the Pegasus Verification System product page.
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