Cadence Certified on TSMC N3, Ultralink on N6, and 3DFabric

Yesterday was it TSMC Technology Symposium. Normally this would have been held face-to-face in April but, like everything else, it has gone virtual. Today, it is the OIP Ecosystem Forum. As usual, Cadence is making some TSMC-related announcements to coincide with the event.

N3

We always have a release about TSMC's latest process node. Our press release team hates writing these since they have to list out all the tools and flows that are supported. I can just get away with saying that the Cadence digital full-flow and custom flow are both fully optimized and certified for N3. I've written plenty of posts about these flows, so I don't feel I need to spell everything out in detail here.

So Cadence tools support all TSMC processes available for design. In particular, all varieties of N3, N4, N5, N6, N7, N16, N22, N28. The more mature nodes are supported too, of course. The "missing" nodes N20 and N10 are also supported, but they are not good choices for new designs.

UltraLink D2D PHY IP on TSMC N7, N6 and N5

Last November, Cadence announced the Ultralink D2D PHY IP. See my post Die-to-Die Interconnect: The UltraLink D2D PHY IP for details. That was in N7. We have since run testchips in N6 and done a full silicon qualification. We have also taped out a version on N5 but don't yet have silicon back from TSMC.

Again, I'll quote from yesterday's press release to make sure it is clear what we are actually announcing:

Test silicon from TSMC with full silicon characterization data is now available, an important milestone for very high-speed, advanced IP. Extensive silicon validation is necessary to guarantee design margins, performance across all process corners, bit-error rate (BER), insertion loss and maximum transmission speed. Cadence is ready to engage with customers now with its UltraLink D2D PHY IP in the TSMC N7 and N6 processes. Cadence also recently taped out its UltraLink D2D IP in TSMC N5 technology and is now working with early adopter customers ahead of anticipated test silicon availability later this year.

UPDATE: InFO and CoWoS

Later in the day, we announced certification of the Cadence flow with TSMC's latest 3DIC technologies, that they now group out under the new name 3DFabric.

Increasingly, a lot of scaling of designs is done using More that Moore approaches with advanced packaging. TSMC has two main approaches, InFO and CoWoS.  InFO stands for Integrated FanOout. CoWoS stands for Chip on Wafer on Substrate. These are the two TSMC system-in-package or 3DIC technologies. In the last year or two, multi-die packages have become one of the hottest areas of design. I noticed at last year's (2019) HOT CHIPS that many, if not most, of the advanced designs were using this type of multi-die packaging. For more on this trend, see my post HOT CHIPS: Chipletifying Designs.

Here are what I pointed to as the drivers for this trend in that post:

• Huge die don't yield as well as the same amount of silicon split into smaller die
• Only some parts of the system require expensive leading-edge nodes
• It's the only way to get enough memory into the system
• It's a way to use the same silicon to address different configurations/markets

Technically, what we announced today was the...

...certification of Cadence reference flows for TSMC’s latest InFO and CoWoS multi-chip(let) packaging solutions, the integrated fanout with RDL interconnect (InFO-R) and chip-on-wafer-on-substrate with silicon interposer (CoWoS-S).

In a bit more detail:

The latest reference flows offer a more efficient DRC signoff/tapeout methodology through preventive and correction design automation, enabled by the Cadence Allegro® package layout technology. Additionally, customers can achieve improved layout automation of InFO-R packages through support for a new standard InFO techfile and design macros in the Allegro Package Designer Plus in conjunction with new in-design DRC validation and 50X performance improvement in advanced de-gassing enabled by the Silicon Layout Option. Finally, the Cadence Clarity 3D Solver has been certified for 3D-EM extraction, including new support for S-parameter model creation for CoWoS-S designs. 

Technology Symposium and OIP

The presentations will be available for replay for 3 months. I don't know if that means you can register and watch them anytime, or if you had to be registered before the event started.

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