The IBM 801, the RISC You've Never Heard of

In a recent post, RISC-V Tutorial, I wrote about the history of RISC-V. The "V" is the Roman numeral for five. Hence, this is pronounced "risk five." With a five in the name like that, the obvious question is, "What were RISCs 1 to 4?". In fact, there was a RISC processor before that, although it is old enough that it is little known today.

IBM 801

The first RISC processor, although it didn't use that name, was the IBM 801. There is a sense in which people today don't count it since it was not a microprocessor. That was because it was developed in the 1970s, long before integrated circuits were large enough to fit a whole microprocessor. Don't forget that even the 1983 Arm 1 filled a whole die without room for an on-chip cache.

The IBM 801 had all the main features of a RISC architecture: a number of processor registers used for all computation, no complex addressing modes, one load, and one store instruction. It was initially 24-bit, but soon that was upgraded to 32-bits.

The visionary of the 801 was John Cocke (see picture). He received the 1987 Turing Award for this work, along with other awards. The 801 was originally designed to run a telephone switch. At the time, the highest performance computer IBM produced was the IBM 370/168, which ran at 3 MIPS. When I was an undergraduate at Cambridge, the University Computing Service ran a very similar machine (I think the IBM 370/165) to run the entire university's computing needs, with maybe 100 or more interactive terminals spread throughout the city. Cambridge University doesn't really have what you would consider a single campus, the university and the city grew up together, and colleges and departments are spread all over, so the terminals had to be spread all over.

To run the telephone exchange effectively, the IBM 801 would need to run at 12 MIPS, so four times as fast as IBM's fastest mainframe at the time. The telephone switch project was eventually canceled, but the results had been impressive enough that IBM continued it as a general-purpose design. The name came from the fact that they worked in building 801, and nobody thought of a better name.

I can't do better than Wikipedia's summary of the influence:

The 801 was extremely influential in the computer market. Armed with huge amounts of performance data, IBM was able to demonstrate that the simple design was able to easily outperform even the most powerful classic CPU designs, while at the same time producing machine code that was only marginally larger than the heavily optimized CISC instructions. Applying these same techniques even to existing processors like the System/370 generally doubled the performance of those systems as well. This demonstrated the value of the RISC concept, and all of IBM's future systems were based on the principles developed during the 801 project.

You might wonder what it means when in that paragraph it says "applying these same techniques to existing processors." After all, you can hardly take an existing processor and redesign it along RISC principles. What actually happened was, I think, a surprise to many people. The compiler for the IBM 801 assumed the basic RISC architecture with register operations, a load, and a store. As an experiment, the 801 PL/I compiler was retargeted to the IBM 360. This is a CISC architecture with a wide range of instructions, such as adding a number in memory to a register or moving one area of memory to another. There were also decimal arithmetic instructions, and a set of instructions for formatting data. So the 801 compiler was retargeted to the IBM 360 but only used the register-register instructions, a single load, and a single store instruction. The code it produced was three times as fast as the "real" PL/I compiler running with the whole portfolio of available instructions.

Or, to be precise, quoting from Cocke and Marstein's 1995 review paper The evolution of RISC technology at IBM:

We discovered that our Model 168, running code generated by the PL.8 compiler, consistently ran between 4.5 and 6 MIPS at a time when it was considered an accomplishment to drive the 168 at 2 MIPS.

All those extra complicated instructions looked good but, in practice, were slower than just using the most basic instructions of all. The 360/370 range was all microcoded, meaning that there was a computer within the computer that actually ran the micro-operations required to handle the complicated instructions. The 801 was not.

Quoting again from the review paper:

This was the key realization: Imposing microcode between a computer and its users imposes an expensive overhead in performing the most frequently executed instructions.

From a lot of work done on instrumenting programs, IBM already knew how important this was. Over half the time in a typical program was spent performing just five instructions: load value from memory, store value to memory, branch, compare fixed-point numbers [integers], and add fixed-point numbers. If you slow those operations down, it is hard to catch up.

The work on the 801 eventually morphed into the RS/6000 workstation and then the Power architecture, the instruction set architecture (ISA) for the current family of IBM Power Mainframes.

For a deeper dive into the 801, see the 1976 monograph The 801 Minicomputer — An Overview.

Patterson Takes a Sabbatical

Some of the next part of the story is covered in my post Fifty Years of Computer Architecture: The First 20 Years. As I said in that post:

Dave Patterson, still at this point an untenured associate professor, took a sabbatical at DEC in 1979. He knew the basic direction of development and knew that the microprocessor people would imitate the mainframe people and use a lot of microcode, as the Intel group in Oregon had been doing. But bugs were always being discovered in microcode and so all mainframes had field-upgradable microcode. Dave realized that they would need to find a way to build field-repairable microprocessors. Being an academic, he wrote a paper on it…but it was rejected. But, rejected paper or not, it was still true: if they imitated the mainframe people and built complex microcoded instruction sets, then they would need to be fixed. 

In the second post of the series, Fifty Years of Computer Architecture: The Last 30 Years, I said:

Dave’s key realization was to get rid of microcode, which had originally been motivated by performance tradeoffs that no longer were true. So instead of having microcode, just run the code directly out of a fast on-chip instruction cache, and stick to just simple instructions. The implementation could have a hardware pipeline. It would then be small enough that a 32-bit microprocessor, and a small cache, would fit on a single chip. That meant signals did not need to cross chip boundaries so it would run at high speed.

RISC-I

That led to the RISC, for Reduced Instruction Set Computer. It is now known as RISC-I but was not at the time. In 1982, UC Berkeley students built the first RISC-I. It was 45,000 transistors in 5um NMOS. The RISC-II, which was a better design, was in 3um NMOS, ran at 3MHz, and the size was 60mm2.

Dave then made what he admits was a mistake. Instead of calling the next two RISC chips RISC-III and RISC-IV, they were named SOAR and SPUR. When Dave told Krste Asanović how much he regretted doing this, Krste said:

Great, we'll just call the next one RISC-V

And they did!

More

Last weekend, after I'd written this post but before it appeared, The Chip Letter's substack published The First RISC: John Cocke and the IBM 801. I doubt either of us has written about the 801 for years, and then coincidentally, we produce two pieces probably written at the same time. Better watch out for a third post on the 801, following Ian Fleming's advice in Goldfinger:

Once is happenstance. Twice is coincidence. The third time it's enemy action.

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