RISC-V Tutorial

27 Sep 2022 • 5 minute read

risc-v logo I keep reading accounts in the media and in the technical press (and YouTube) that misinterpret what RISC-V is. So today's post is going to explain that.

Let's get the big thing out of the way; RISC-V is NOT a processor. I'll say that again to emphasize the point: RISC-V is not a processor.

So if RISC-V is not a processor, what is it?

The RISC-V ISA

Before getting to that, let's get to pronunciation: RISC-V is pronounced "risk five".

RISC-V is an Instruction Set Architecture or ISA. In a sense, this is a contract between the software and the hardware. If the hardware sticks to the ISA correctly, then the hardware will run all the software correctly. In the 1950s, there was no such thing as an ISA, just an instruction set. Nobody had built multiple computers that ran the same code. That all changed on April 7, 1964, when IBM announced the System/360, its instruction set, and four computers at different price/performance points that would execute it. That ISA is so long-lived that even today, almost sixty years later, code written for those early machines will run on the latest IBM Series Z mainframes.

RISC-V was originally developed by a group of grad students under Krste Asonaović at UC Berkeley. They wanted to do research on computer architecture, but the obvious candidates for an ISA to use, Arm and x86, were way too complex (and legally encumbered). So they rolled their own with no Dr. Evil expectations of taking over the world. This started in 2010, so twelve years ago. I have written about RISC-V many times, most recently in:

Unlike most ISAs, such as Arm or x86, the ISA is completely open. Anybody can use it for free. Almost all work in academia in computer architecture is now going on using RISC-V. Hennessey and Patterson's two books on Computer Architecture have been moved over to RISC-V. Almost all work in security is now going on on RISC-V since you can (often, see below) inspect the details of the processor.

The team that developed the RISC-V ISA set up the RISC-V foundation to own the ISA and handle how it was standardized. I made it sound like it is a single ISA, but in fact, it is designed with modular extensions. For example, there is a floating point extension. You don't have to implement a floating point, but if you do, the extension tells you how that part of the ISA works. I think that the organization is now called RISC-V International since it relocated its HQ to Geneva, Switzerland.

I first came across RISC-V at EDPS back when it was still held in Monterey. I wrote about it in RISC-V—Instruction Sets Want to Be Free. This was in 2016, and I realized RISC-V would be significant and that Breakfast Bytes should write about it So I attended the RISC-V Symposia, initially on the Google campus, then in Shanghai, Milpitas, and finally it got big and moved to the San Jose Convention Center where it still is today. This year's RISC-V Summit is December 14th and 15th.

RISC-V Cores

If you want to design an SoC with a RISC-V processor, then the obvious question is, where do you get one from? There are three main groups.

Build It Yourself

The first option is to build it yourself. The RISC-V ISA is free of licensing and royalties, so you can just go and do that. For example, Esperanto did that, as discussed in my post HOT CHIPS: Esperanto's Dave Ditzel and 1000 Minions.

You probably don't have such unique needs as to justify the time and expense of designing your own processor from scratch, so I seriously doubt that this is an option you should even consider.

Open Source

There are many open source RISC-V cores available from both academia and industry. Many of these you can just get from GitHub. I assume these are of variable quality and certainly come with variable amounts of support. SiFive for one, has open source cores and will sell you services to help you use them. Codasip too.

Proprietary

Thirdly, you can buy a core. The main vendors that I know of, just based on their attendance at RISC-V summits over the years, are:

SiFive: this was founded by the team that defined the original RISC-V ISA and is based in silicon valley
Andes: based in Taiwan, they went all-in on RISC-V and switched away from their proprietary instruction set several years ago
Codasip: basedi in Brno in Czechia. They have cores and a wide range of services

There are many more. See the slide at the end of this post. One thing that is unique about RISC-V is that you can choose the processor ISA (that is, pick RISC-V) and then decide between multiple sources of cores, all of which should work to run your software stack.

Derivatives

No matter which approach you take, you have the choice of just implementing the core the way it comes out of the box, or you can customize it in some way. A popular way to customize right now is to add some sort of AI accelerator hardware to work with the RISC-V cores. At the recent AI Hardware Summit, several big names announced that they would be switching to RISC-V so that they could focus their efforts on the neural network blocks where they can differentiate their solution from the competition. I expect to see more of this. If the instruction set of a processor is not exposed to the user, like the application processor in an iPhone or the processor chip in a server, there is no real reason not to use RISC-V other than inertia.

Summary

Krste describes that the "modest goal" of RISC-V is to become the industry-standard ISA for ALL computing devices. I first heard him discuss this back in his 2016 DAC Sky Talk. It seemed plausible but a long way off. But here is his view from 2020:

There is way too much going on in the RISC-V world to fit it all in one slide, but here is his most recent attempt:

Video

I actually wrote this last weekend, and just yesterday a video appeared with Krste Asanović discussing the history and future of RISC-V (plus a commercial for SiFive's cores at the end). The whole video is about 30 minutes long.

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