The State of the RISC-V Union, part II

This is part 2 of my post on DAC and RISC-V from December. The first post is here. This post will cover Krste's presentation and then Calista back at the end to wrap up the conference and talk about the future.

Krste

Krste started on a similar note to Calista in his "State of the Union" keynote:

The State of the Union is strong!

Dave Patterson has said "RISC-V is inevitable". We used to joke about how RISC-V would take over the whole industry...and now it's obvious that RISC-V is going to take over the whole industry. It's such a good idea. People see that this is how things should be done at the instruction-set level.

Krste talked about how RISC-V is just an ISA, but it has engendered a lot of open-source cores, commercial cores, and internal cores. And a big thing for people designing those cores is that they don't have to worry about the software since there is a huge portfolio of both open-source and commercial software available. The ISA is the contract between hardware and software, so by standardizing that it has enabled a lot of developments on both sides of the divide.

A big difference between RISC-V and the two main alternative ISAs that ship at scale is the business model. For example, if you want commercial core IP for an Arm processor, then it is available. But only from Arm. For an x86, forget it. Neither Intel nor AMD (nor Via) is going to give you IP, although in his announcement of the Intel Foundry business, CEO Pat Gelsinger said that would change...but presumably only if you use Intel as your foundry.

There are lots of commercial vendors of RISC-V IP, you have to pay for them but they're supported, the companies stand behind them. There are more vendors now than any other ISA ever in history. And that number keeps growing.
...
RISC-V is the ISA that likes to say "yes".

But saying "yes" brings its own challenges since there is demand for RISC-V everywhere, at every performance level from "low to ludicrous". There are requests for every feature that has ever appeared in any other ISA ever, but there are real-world constraints. One is fragmentation versus diversity. Fragmentation is bad, when you do the same thing two different ways for no good reason (such as half the world driving on the left and half on the right, meaning many cars have to be produced in two different versions, which is an unneeded cost to society). Diversity is good, solving different problems (such as a bicycle and an airplane...you can't cycle across an ocean nor take a plane to the supermarket).

A few powerful forces keep fragmentation at bay:

• Users: nobody wants to repeat vendor lock-in
• Software: nobody, not even a nation-state, can afford their own software stack. Upstream open-source projects only accept frozen and ratified Foundation standards
• As gaps get filled in the ISA it reduces the motivation for fragmentation by people who "need a feature but who have to ship a product so they do their own thing just to get to market"

As to managing diversity, there is the base, standard extensions, and custom extensions. This obviously leads to a combinatorial space of options. So to keep things under control there are ISA profiles. The first three are RVI (basic), RVM (microcontroller), and RVA (application processor). For compilers and the toolchains this simplifies things in terms of giving them guidance on what they should prioritize support for. There are also platform standards, which is about the hardware. There is more to a system than just the ISA: memory map, controller, reset, boot. The initial focus is on OS-A platform for Unix-like OS. A standard operating system distro should run on any processor that meets this standard.

Krste moved on to how many ISAs are on one SoC. There is an application processor, usually Arm. Graphics processors, image processors, radio DSPs, audio DSPs, security processors...and more. Each with a unique software stack. The reason for this is that the application processor ISA is too big and inflexible, but also IP is bought from different places and those vendors can't always put a proprietary ISA in its product since it doesn't have the right to resell it. And:

Engineers like to build their own ISA and that's generally a bad idea

Software is one of the biggest costs in a heterogeneous SoC, and it has always been a vision to use RISC-V for all cores on an SoC for all SoCs. Lots of reduced costs for toolchains, training, development cost, and more.

We're going to have thousands of cores on an SoC. How do we manage them? Power management, task allocation, accelerators, memory allocation, interrupt routing...and the biggest item of all, how to compute securely everywhere.

Krste wrapped up with a look to the future. 2021 was the year he considers RISC-V stopped playing catch-up and in the next five years will start leading the industry. It is a new open standard and is driving innovation in software toolchains, software/hardware co-design, SoC/chiplet methodologies.

There have really been five eras in instruction sets:

• Every computer had its own instruction set, no winners
• IBM 360, winner of the transistor era (with multiple computers running the same ISA)
• x86, winner of the microprocessor era (with semiconductor node after node enabling higher performance with full binary software compatibility, while adding new instructions)
• Arm, winner of the soft-core IP era (with several versions of the instruction set)
• RISC-V, winner of the <insert your best era-name here> era. With...well, sit back and we will see

Calista (again)

At the end of the summit, Calista came back on to present Where is RISC-V Going?

She started with an industry view of where RISC-V is showing up. In academia, victory is already total.

• During the summit:
  • SiFive announced the fastest high-performance processor
  • Google using RISC-V for more granular workload acceleration
• Datacenter
  • Alibaba RISC-V Xuantie processor line including four open-source processors
  • Imagination RISC-V CPU family
  • Seagate hard disk drive controller
  • Ventana performance chiplet approach to datacenter design
  • Intel Nios processor (for its FPGAs fka Altera)
• Telecom
  • Andes 64-bit RISC-V processor adopted by SK Telecom for AI products
  • Alibaba PLCT lab has ported Android 10 onto their RISC-V core emulated in QEMU
  • Google Pixel 6 Titan M2 in-house designed processor with extra speed, memory, and resilience to advanced attacks
• Automotive
  • Imagination Technologies' GPU linked to RISC-V core for ASIL-B leve designs
  • IAR Systems extended functional safety to RISC-V core of Nsitexe, a subsidiary of Denso (Tier-1)
  • Renesas and SiFive joined developed next-generation RISC-V cores for automotive
  • Renesas and NSI-TEXE announced automotive SoC with RISC-V based parallel co-processor
  • Europe's GaNext project to simplify designing power convertors (for car charging) with Gallium-Nitride (GaN)
• Consumer and IoT
  
  • Huawei Hi3861 RISC-V board for Harmony OS developers
  • Earbuds from Bluetrum (millions shipping every month)
  • Zepp Health/Huami wearable manufacturer OS supporting RISC-V reference models
  • GreenWaves ultra-low-power GAP9 hearables platform
  • Microchip released the first SoC FPGA development kit based on RISC-V
  • RISO Lab announced Pico Rio, and affordable RISC-V open-source small-board computer
  • SiFive world's fastest development board for RISC-V personal computers
• Artificial Intelligence (AI)
  • Esperanto with 1,000 core AI accelerator
  • StarFive release the world's first AI visual processing platform
  • Andes released superscalar multicore and L2 cache-controller processors
  • NVIDIA CUDA support on the Vortex RISC-V GPGPU enables scaling from 1 to 32 core GPU based on RV32IMF
• Edge Computing
  
  • Seeed Studion's SiSpeed MAIX, a RISC-V 64 AI board for edge computing
  • Micro Magin's fast 64-bit RISC-V core (5GHz, 13,000 coremarks, at 1.1V)
  • Wester Digital SweRV core enables spectrum of compute at the edge
• High-performance Computing (HPC)
  
  • European Processor Initiative with first AI accelerator chip taped out September 2021
  • Technical University of Munich (TUM) with a quantum cryptography chip
  • Tactical Computing Labs test suite for GCC and LLVM focused on HPC
  • Cortus high-performance out-of-order processor core for the European eProcessor Project
  • De-RISC HW/SW/ platform for multi-core RISC-V SoC for safety-critical aerospace

Calista said that RISC-V has:

passed the inflection point from vision to adoption, we have arrived and we are not slowing down

She wrapped up with laying out the strategic roadmap for the coming years. And also pointed out how many RISC-V job openings there are:

there is opportunity to build your career here

A Prediction

Just like once reduced instruction sets were conceived by Dave Patterson and John Hennessy there has never been a new CISC ISA ever, I predict that there will never be another ISA that is not based on RISC-V. It is already clear that victory is going to be total except for the legacy instruction sets that already exist with wide adoption. Like Tensilica. Oh yes, and Arm and x86. And, in specialized areas like automotive, several others that you've probably never heard of, like the NEC V850 (now Renesas, of course).

Videos

Here are the two presentations (both around 15 minutes).

Krste:

Calista #2:

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