RISC-V: The Next Ten Years

The annual RISC-V Summit (virtual, of course) was in early December. You can read my first report in my post The 2020 RISC-V Summit. The second day started with a keynote by Krste Asanovic, the lead of the team that defined the RISC-V ISA.

Krste Asanovic

Krste pointed out that instruction sets last a long time. Decades. The first true ISA was the IBM 360 ISA and it is now 56 years old. The Intel x86 is now 42 years old. Arm is 35 years old. Even RISC-V, the new kid on the block, is over 10 years old. Interestingly, that doesn't seem to apply to specialized processors like DSPs, GPUs, or image processors. Their instruction sets seem to come and go.

Krste pointed out that:

It's easy to think things move slowly until you look back. Deep learning only emerged in 2012, it just wasn't a thing 10 years ago. Spectre and Meltdown emerged even more recently.

He moved on to look at the future, the next 10 years.

• There will be new security threats...but don't what.
• New application areas will become significant...but don't know what.
• We'll need to start at least on RV128 definition (128-bit version of RISC-V ISA).
• RISC-V will increase adoption throughout computing.
• There will be new specialized processors, but based on RISC-V rather than a proprietary base.

So Krste feels that their "modest RISC-V project goal  "which is "to become the standard ISA for all computing devices" is increasingly happening. Already, RISC-V has more commercial core providers than any instruction set in history. In effect, "everyone gets an architecture license". But the crown jewels are the software ecosystem that is building up around the ISA.

The diagram above shows some of the ecosystem. On the bottom is hardware, at the top is software. In the middle is the RISC-V ISA, which is the contract defining the interface between software and hardware. Also, that's where RISC-V International sits with its own mini-ecosystem defining the ISA and addressing compliance.

Another development going forward is the creation of architecture profiles. These will define a group of extensions required for those profiles (and others explicitly not required). The idea is to make things easier for software developers (for example, what is required to boot Linux). Profiles may only include ratified extensions at the date of creation. There are two profiles under development so far:

• RVA19 application processor for 2019
• RVM19 microcontroller for 2019

The next target is RVA21 and RVM21, expected to be finalized for the December 2021 RISC-V Summit, and can include anything in the spec by then.

Basically, RISC_V will broaden to new areas, and RISC-V International (he is chairman) is organizing to scale as RISC-V takes on more application areas, with more members and more contributors.

Rick O'Connor

Next up was Rick O'Connor (who was Calista's predecessor as CEO of RISC-V International). He is now CEO of OpenHW Group. As he put it:

We haven't yet cracked the nut of open-source hardware being used in high-volume applications.

Part of the problem, Rick feels, is that there are too many cores. Too many cores is a barrier to adoption, a sort of paradox of choice. The issue is "how do we establish critical mass around a handful of open cores."

He had a chart with many of the cores, to show the issue. Sorry that it's so hard to read—but you get the idea just from the size of the table.

He gave a bit more detail on OpenHW (Cadence is a partner). OpenHW is a not-for-profit global organization, driven by its members and individual contributors, where HW and SW designers collaborate in the development of open-source cores, related IP, tools, and software, such as the Core-V family of open-source RISC-V cores.

The initial two cores families are:

Fireside Chat

Next up was a fireside chat moderated by Nitin Dahad, Editor-in-chief of EETimes and Embedded.com. The three fireside chatters were:

• Dave Patterson (who needs no introduction, but if you don't know who he is, see my post Dave Patterson on Becoming a Computer Scientist...and Going Directly to Happiness).
• Krste Asanovic (who also needs no introduction, especially since he showed up giving the first keynote in this post).
• Chris Lattner, the President of Product and Engineering at SiFive, probably the most prominent of the RISC-V startups, not least since the creators of the RISC-V ISA all work there (Krste is the chief architect).

Q: So where are we now?

Krste: We are way beyond anything we ever imagined. People are using RISC-V in places we never imagined. So it is way beyond any expectation that we had at the time.

Dave: About six years ago we started to get interest from companies, not just academia, and we saw that there was a thirst and we saw why, so we changed our expectations to "world domination".

Chris: iI's super-exciting. There's been lots of success but there is still lots of road ahead of us.

Q: Where do you think we are right now in terms of the mainstream? Is it there yet? Is it replacing other architectures?

Chris: I think RISC-V is far better suited for many applications than x86, since it scales both up and down. But RISC-V is broader than just the ISA, standardizing a whole slice of the ecosystem. It is already becoming mainstream. There is a groundswell of designs that take time to get to market, but it’s very much there.

Krste: Open-source software community people are used to things moving quickly. But in chips it is a two-to-three year process from starting a project, to shipping actual products. NVIDIA, Qualcomm, Samsung all shipping products with RISC-V inside. You will see more in the next year or two.

Q: Why is there the narrative that RISC-V has “yet to go mainstream”?

Dave: RISC-V is a revolution for hardware. Up until RISC-V ISAs have been proprietary and tied to the fortune of the company. For example, the MIPS architecture is now on its seventh company. Plus there are competing organizations that are seeding doubts.

Krste: To be truly mainstream is when you become well known to the consumer. But companies only seem to get publicity when there is an issue.

Dave: Why did everyone get to know the word Pentium? Because of the Pentium floating-point bug. Maybe we need a disaster so it’s in the newspaper!

Q: What about the business model? Is there something wrong there?

Krste: I think NVIDIA is making quite a bit of money with RISC-V. RISC-V is an open specification, not an open-source processor. We build on lots of open standards, but that doesn't mean you can't make money. Ethernet is open. How can Cisco make any money? The great thing about being open is that you enable open-source and we can have open-source hardware.

Q: What are the implications for security?

Dave: It’s embarrassing how bad security is. We are not going to have a software-only solution, that hasn’t worked. Changing the instruction set is a really slow process. Open hardware implementations and FPGAs so that the security community can innovate and try it are an enabler. DARPA embraced that and has four different architecture attempts, put them on the internet, and offered a bounty for finding bugs. There is a capability-based architecture, a security monitor from Lockheed, a version of Enclave using keystone project from MIT. And one from Michigan. All four used FPGAs and RISC-V. This was July to September so I’m looking forward to hearing the results.

Q: I was in a conversation with someone in Zurich who was telling me RISC-V inherently enables strong security?

Krste: We did think about security early on, and the extra mode we added was a machine mode below supervisor mode so you don’t need to trust the operating system. It's a very lightweight layer underneath. But there is a lot more to do. There is a Cambrian explosion of security ideas for architecture, some of which are very intrusive. But we are enabling experimentation.

Q: Can you see a standard ecosystem to enable people to build better security?

Chris: The investment is typically at the high end, but security affects everything. Even the tiny embedded cores. Specter and Meltdown came out of nowhere, but they need to be addressed at every point in the space. [Actually, Spectre and Meltdown depend on speculative execution so don't actually affect the lowest end cores]. A classic proprietary core targeted at a small footprint that has been sitting on the shelf for 10 years gets no interest from the vendor in revisiting. RISC-V moves much faster due to the multi-source approach with multiple vendors.

Q: Let's segue to a difficult question. How far are we behind Arm and Intel in terms of tools and support?

Chirs: There's good news and not-yet-done news. LLVM, GCC, Linux all have good support for RISC-V. A couple of challenges are that Windows and Android don’t run on RISC-V. Vectors are still a new technology and lots to be done there. Some software will need to be rethought and look at vectors in a new light. Machine learning is well prepared since modern compilers can handle it. Overall, it is exceeding expectations.

Q: Architecture, security, software, tools. How about applications? What is RV really good for specifically?

Dave: I bet the Arm people would say Arm is universal, but that applies to RISC-V, too. The killer mistake in architecture is not having enough address bits. But RISC-V already has 128-bit address space baked in. When you teach a course, you always subset the architecture (e.g., MIPS) but that is embraced officially in RISC-V. This is a new characteristic of computer architecture, with only 47 instructions in the base set. Formally defined industrial strength, so the security people love it. It is so much easier to handle than any other architecture, inspired by pedagogical aspects.

Krste: In ecosystems like Android or Windows there is a whole software base coded to a specific ISA. People still run Unisys mainframe stacks. More important are the new areas. In the future, most are new stuff. Nobody is designing x86 into any new stuff, it has its place. The big deal with RISC-V is not the technology, it is the business model. If you are building something big, why would you trust a signal vendor, why would you not use RISC-V. Up in the C-suite, people are looking at this as a long-term business decision. Monopolies are good at extracting money from people and C-suite execs know this.

Q: When someone has invested a lot then is it difficult to move?

Chirs: RISC-V supports all the standard toolsets, so there is some retraining but most of the toolsets are there. We should be looking to reduce the friction of migration moving from existing ecosystems that we know are out there.

Dave: Binary compatibility is no longer as important as it once was. In the PC era, the x86 was overwhelmingly important. In Android and Apple, it is still important, but everywhere else it is not. The future is not proprietary instruction sets and binary compatibility.

Krste: Apple just made a big ISA transition, and with the right technology it is not a barrier to moving. In the beginning, we were trying to create a good solution, but now making it easy to transition is another goal. This is a big demand from the community, so even if adding things is exciting, we need to think twice about migration.

Q: What is the favorite thing you’ve seen that is also commercially viable?

Dave: I don’t keep up with products, but the thing I’m most excited about is the security investigation.

Chris: Diversity of the ecosystem is the most exciting. The subset ability, the customizability, application to different domains.

Krste: Growing up in Britain I was a big fan of Dr. Who, and now we have the SiFive Dr. Who mass-market product for kids to teach them how to program in RISC-V.

Software Ecosystem

To wrap up, here are a couple of slides from Yunsup Lee's presentation. He is CTO of SiFive and one of the creators of the RISC-V ISA. These summarize the state of the software ecosystem for RISC-V.

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