CadenceLIVE Boston: State-of-the-Art Heterogeneous Integrated Packaging (SHIP)

Congress and the military love to come up with cute acronyms for programs, and so the Navy has come up with SHIP (after all, they are the Navy), which stands for State-of-the-art Heterogeneous Integrated Packaging for RF. I wrote about this topic (without the RF bit) earlier this week in my post titled 3D Heterogeneous Integration (3DHI).

At CadenceLIVE Boston, Ted Jones of Qorvo summarized the state of the SHIP program, followed by Cadence's Paul Mosinskis who took a deeper dive into Cadence's technology for designs for multiple-die in the same package, aka Heterogeneous Integration or 3DHI.

UPDATE: Ted had Covid and so it was actually Matthew Poulton who presented in his place.

Matthew Poulton

The program's goal was "Establish domestic, secure, SOTA, cost-effective, heterogeneously integrated packaging". Or, in another level of detail, "Assembly and packaging of multiple, separately manufactured integrated circuit die into a single package".

It is a three-phase program spanning four years, kicked off in October 2020. It is funded by the OUSD (office of the undersecretary of defense) and executed through Navy Crane. It fits into the DoD's Trusted and Assured Microelectronics (T&AM) strategic initiative.

Qorvo is central to the program, having extensive commercial experience in packaging coupled with over 30 years of working with the DoD. So SHIP is adapting Qorvo's Open Foundry Model and also is re-shoring its flip-chip high-volume manufacturing capability.

The above diagram shows how the Qorvo Open Design Center (DC) and the Assembly & Test Center (ATC) work together. Note that components such as ICs can come from non-Quorvo sources, although the plan is to maximize domestic content. The design function only applies to heterogeneous packaging, not to the design of integrated circuits (chiplets) themselves. One important part of the flow is that Qorvo is creating Assembly Design Kits (ADKs) and Design Rule Checks (DRCs) ensuring customers create manufacturable designs for SHIP-RF ATC.

SHIP Design Center, the center of the diagram above, will be the focal point where customers will be able to:

• Access design simulation, verification and layout tool kits for design at their facilities
• Collaborate and/or co-design with project partners, including Qorvo
• Architect next-gen system in package (SiP) platforms using SHIP DC IP block libraries
• Design and verify circuit and layout using an integrated mixed-signal EDA platform
• Validate SiP prototypes using SHIP DC multichannel and mixed-signal test systems
• Project-manage programs with advanced life cycle management tools
• All in a managed ecosystem where project IP is secure and segregated from other SHIP programs

This does not all exist yet. The above timeline shows the SHIP-RF roadmap (click to enlarge).

As part of the program, a new SHIP-RF ATC is being created in Richardson TX, an extension of Qorvo's existing Advanced Microwave Module Assembly or AMMA. This will:

• Create a highly automated, US-based, assembly and test factory offering access to SOTA manufacturing technologies at commercially competitive pricing
• High throughput and automation ➔ domestic, secure, and cost-effective
• Build on Qorvo’s proven commercial SOTA packaging technologies running at HVM rates offshore
• Setup and qualify highly integrated packaging technologies
• Leverage Qorvo’s microelectronics factory scale in Texas

Matthew summarized the presentation and the state of SHIP-RF by emphasizing that it is "real". Use-case demonstrators are being developed to pipe-clean the advanced packaging business process, exercising both the design center and the assembly and test center. Assembly design kits (ADKs) have been developed for 2D multi-chip modules (MCM) and for 2D RF SiP small die. In the works are 2D RF SiP large die and double-sided molded BGA (DSMBGA). The above GANTT chart shows the various subproject timelines all the way to the end of September 2024.

Paul Mosinskis

I've covered Cadence's capabilities for 3DHI before, so I won't go over the whole of Paul's presentation, just a few key slides. 

The diagram above shows the three legs of the stool, perhaps the most important being that there is a single golden hierarchical schematic to drive the whole design and verification process. This results in a full laid-out and verified design, on the left shown in 2D, on the right shown in 3D.

A lot of RF verification can be done, and perhaps one of the most important aspects of any 3D package is the thermal aspect. The diagram below shows the output from Celsius, and to everyone's surprise, the most critical thermal challenge is the regulator.

Summary

Pulling everything together, the diagram above shows the Qorvo SHIP-RF design flow vision.

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