SPIE is the international society for optics and photonics, with the purpose of “advancing an interdisciplinary approach to the science and application of light”. What everyone calls "spie" (pronounced "spy"), however, is actually the SPIE Advanced Lithography Conference. The name SPIE doesn't stand for anything anymore. Originally the P was photography, but this was back in 1955, so pre-IC. I assume there was no advanced lithography conference in those days, or if there was, it was still the original meaning of lithography (lithos or λίθος means stone in Greek), a printing process using a flat stone with the unprinted areas marked out in grease so the ink would not stick. This printing process is still used, although with a photographic image transfer to metal sheets rather than stones. For more about my experience with that sort of lithography, see my post Jobs: Printer, Baker, Chocolatier, Caver.

There is a lot of similarity between the modern lithographic process for printing with how photoresist works. And if stones and grease sound weird, try explaining the droplet generator and the lasers in an EUV light source.

The SPIE Advanced Lithography Conference is 24th to 28th February in the San Jose Convention Center.

Plenary Session Keynotes

As usual, the conference opens with a plenary session on Monday morning with 3 keynotes.

It seems to be almost obligatory for conferences to have a keynote about quantum computing these days. DesignCon recently had one. Dario Gil of IBM opens the conferences (after the welcome and awards) with The Future is Quantum. He gave one of the keynotes at last year's Design Automation Conference, so if you want to get a preview of some of what he will discuss, you can read my take on that in DAC Tuesday: IBM's AI, Jay's Wall Street View, Lip-Bu's Chat, Monster Chips.

Dario is followed by Jeongdong Choe of TechInsights with a presentation titled 3D NAND Flash Technology: Roadmap, Process, Design, and Challenges. One of the biggest transitions in semiconductor manufacturing of the last decade has been the switch from planar NAND flash to 3D NAND flash (although usually people just say 3D NAND). This requires stacking lots (like 96) layers of memory on top of each other, and then doing one of the hardest steps in all of semiconductor, etching a hole through the whole stack with an aspect ratio of 60-80 to 1. That's like building a skyscraper on a 30 foot by 30-foot lot. Jeongdong has a background at both SK-Hynix and Samsung, two of the three big names in NAND flash today.

A new cast, but the same topic for the 3rd keynote titled Patterning in the Stressful World of 3D NAND. I don't know if this is a panel session, a lot of short presentations, or a long presentation with lots of authors. They are ASML's Steven Steen, Michael Kubis, Jan Willem Cromwijk, and Hans Kattouw, along with Lam Research's Bart van Schravendiijk, and Yongsik Yu. One of the topics that will be discussed is the high aspect ratio etch that I mentioned above.

EUV

The biggest challenge in lithography is to improve EUV for second-generation 7nm processes, and get it ready for 5nm and beyond. For a recent post of mine on the current state of play, see IEDM: EUV, the Road to HVM and Beyond from last month. The big challenge is dealing with stochastics, randomness in the manufacturing process since we are down to small numbers of molecules and photons.

If you are interested in recent developments, then don't miss the big sessions on the EUV track. 4 and 5 on Tuesday from 8am to just before noon on the EUV track, and sessions 8 and 9 at the same times on Wednesday morning:

• Session 4: Stochastics and Exposure Mechanism
• Session 5: Order from Chaos: Stochastic Modeling
• Session 8: EUV Patterning and Etch
• Session 9: EUV Masks, Defects, and Pellicles

Cadence @ SPIE

Cadence and its customers are presenting 3 papers this year. They are all in the Design-Process-Technology Co-optimization for Manufacturability track.

A Novel Design-for-Yield Solution Based on Interconnect-Level Layout Improvements at 7nm Technology Node [10962-3]
Wednesday, February 28, 8:00am – 10:00am / Conference 10962, Session 1
Authors: Jaehwan Kim, Sangah Lee, Byungchul Shin, Junsu Jeon, Jin Kim, Byung-Moo Kim, Jae-Hyun Kang, Seung Weon Paek, SAMSUNG Electronics; Piyush Pathak, Frank E. Gennari, Philippe Hurat, Ya-Chieh Lai, Cadence.

Pattern-Aware Diagnostics: Using High-Performance Pattern Analysis to Identify Defect Root Cause [10962-8]
Wednesday, February 28, 10:30am – 12:10pm / Conference 10962, Session 2
Authors: Jason P. Cain, Abdullah Yassine, Moutaz Fakhry, Advanced Micro Devices; Piyush Pathak, Jeffrey E. Nelson, Frank E. Gennari, Ya-Chieh Lai, Cadence.

Hotspot Detection Using Squish-Net [10962-27]
Thursday, February 29, 1:30pm – 3:30pm / Conference 10962, Session 7
Authors: Haoyu Yang, Piyush Pathak, Frank E. Gennari, Ya-Chieh Lai, Cadence; Bei Yu, The Chinese Univ. of Hong Kong.

Exhibits and More Details

Cadence is exhibiting at booth #213. Hours are Tuesday from 10-5 and Wednesday from 10-4. For more details see our SPIE page.

To attend the conference, go to the SPIE registration page.