One of the challenges in leading-edge nodes today is the resistivity of the interconnect. One day, new interconnect materials such as ruthenium (Ru) might help, but for now, we have copper interconnect, which requires a liner made from a relatively high resistance barrier metal, typically tantalum-based, taking up a fair bit of the cross-section of the interconnect channels and lying across the bottoms of the vias. For a look at the future of interconnect, and more details on the current copper/liner issues, see my posts from earlier this year IEDM: The World After Copper and ITF: CFETs and New Interconnect. Bottom line, for the time being, is that timing is more dependent on resistance than capacitance in the interconnect, the other way around from most of the history of integrated circuits. That makes IR drop analysis increasingly critical during timing signoff.

Tempus Power Integrity Solution

One impact of high-resistivity interconnect is that everything depends on everything else. Timing is obviously affected by interconnect resistance, but interconnect resistance in the power and clock networks affects timing, too. This means that you can't just check each aspect of the design on its own. Today, Cadence announced the Tempus Power Integrity Solution, the industry’s first comprehensive static timing/signal integrity analysis and power integrity analysis tool.

This is an integration between the Tempus Timing Signoff Solution and the Voltus IC Power Integrity Solution. The tight integration means that designers can lower IR drop design margins without sacrificing signoff quality, resulting in improved power and area. Early users found that the integrated product correctly identified IR drop errors prior to tapeout. This improved maximum clock frequency in silicon by up to 10%. The integration means that designers can accurately assess the impact of IR drop on timing, speeding design closure.

At 7nm and below, interconnect resistance is very significant, and so accurate analysis of IR drop is essential to avoid silicon failures. As always, the alternative to accuracy is to use bigger guardbands, but that risks giving up a lot of the benefits of using that process node in the first place. Integrating the Tempus and Voltus solutions increases accuracy, and thus allows designers to use the full performance of the process without risk of failure. But it is not just smaller IR drop margins. The tool contains intelligent activity generation and direct calculation of the timing impact of IR drop, reducing the need for larger safety margins, and so optimizing power and area.

There is vectorless activity generation that automatically develops activity vectors for full coverage while also exploring potential failure scenarios on voltage-sensitive paths, improving signoff IR drop analysis reliability. The proprietary vectorless-based algorithm identifies voltage-sensitive paths: sensitivity analysis combined with proprietary algorithms developed through machine learning (ML) techniques efficiently identify critical paths most likely impacted by IR drop. The Tempus Power Integrity Solution’s methods ensure a high degree of IR drop analysis coverage without requiring extensive, time-consuming vectors.

Of course, the purpose of the analysis is to find and fix potential IR drop failures early in the design cycle and fix them automatically.

Martin Frederick Jr, a fellow in the physical design group at Arm, was one of the initial users and  found better results than with the traditional flow:

IR drop analysis is a key signoff technology that is increasingly critical, especially for today’s high-speed chips operating with highly resistive lower metal layers, Our evaluation of the Tempus Power Integrity Solution highlights that Cadence’s integrated approach provides better coverage than traditional vector-based flows for reasonable amounts of compute.

More Information

For more information see the Tempus Power Integrity Solution product page.

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