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At CadenceLIVE Americas back in June, GlobalFoundries presented a case study on using a Tensilica ConnX B10 DSP in their 22FDX process in a design that had to meet automotive grade 1 requirements. The study was to see what was the impact on power, performance, and area due to the additional signoff requirements.
The 22FDX process is a 22nm derivative of the 28nm FD-SOI process that GF licensed from STMicroelectronics. For more details, see my posts:
The ConnX B10 DSP is used for various things in the automotive industry, especially the signal processing associated with radar and lidar. For more details, see my posts:
GF likes to position itself as the only global manufacturer (it's in the name!) since they have fabs in the USA (Malta, NY; Burlington, VT; and East Fishkill, NY), Asia (Singapore), and Europe (Dresden, Germany). In fact, its fab 1 in Dresden is apparently the largest cleanroom in Europe. And that is where 22FDX is manufactured.
22FDX (and FD-SOI in general) has the capability of body bias. This can be used to fine-tune the performance (by using positive body bias) or leakage (by using negative body bias). This can be done in several ways:
For more about body bias, see the above-linked posts about 22FDX reference flows. For this case study, adaptive body bias was used.
Automotive grade 1 has additional digital design guidelines beyond what is required for a consumer product. It is well known that they want to get to zero defects and so a lot of attention has to be paid to variation using LVF (liberty variation format) libraries. For automotive, they use higher sigma values and this extensively affects setup and hold checks around flipflops. For automotive grade 1, the junction temperature range is bigger, 150°C versus 125°C for commercial grade, at the high end and -40°C at the low. Along with higher temperature comes higher leakage. Cars last for a long time, 20 years or more, so the lifetime of the cell and the aging affects are more severe, the cells become slower and so additional aging derates are required, which is all handled in Tempus STA. Electromigration (EM) is also worse at the higher temperature, which is especially important in design of the clock trees. All these stricter signoff requirements required to ensure the robustness of the design feed into PPA, generally making things worse (lower performance, higher power especially leakage, bigger die). Obviously, all the IP (standard cells, memories, etc) need to be qualified for automotive.
The diagram above shows the floorplan for the processor along with a few of the most critical configuration parameters for memories, caches, and so on.
The flow used Cadence's Genus, Innovus (including iSpatial, ccOpt etc), Quantus, Tempus, Joules, and Xcelium technologies. There are a few remaining DRC errors but GF believes they are fixable and do not affect the PPA information.
Above is the IR map with body bias taken into account.
Four versions of the design were created, all with the same floorplan:
These designs allow both the effect of adaptive body bias on the design, and the two sets of conditions allow an analysis of the extent to how automotive conditions affect the overall PPA of the test case.
The table above shows the results, where you can dive into the details if you want. The bottom line is that adaptive body bias compensates almost completely for the automotive grade conditions, with no impact on area. There is a 50% reduction in leakage power.
The tool flow worked:
But the key findings that the project set out to determine were:
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